Symbol: _reg_write_4
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
65
_reg_write_4(SH4_PCTRA, 0);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
67
_reg_write_4(SH4_PCTRB, 0);
sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c
84
_reg_write_4(SH4_PCTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c
102
_reg_write_4(SH4_PCTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c
153
_reg_write_4(SH4_PCTRA, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
244
_reg_write_4(SH4_WCR1, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
247
_reg_write_4(SH4_WCR2, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
250
_reg_write_4(SH4_WCR3, reg);
sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c
253
_reg_write_4(SH4_PCR, reg);
sys/arch/evbsh3/evbsh3/machdep.c
368
_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
388
_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
403
_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
407
_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
420
_reg_write_4(SH4_MCR, BSC_MCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
482
_reg_write_4(SH_(CCR), 0x1);
sys/arch/hpc/stand/hpcboot/sh3/cpu/sh3.h
103
#define SH3_MMU_DISABLE() _reg_write_4(SH3_MMUCR, SH3_MMUCR_TF)
sys/arch/hpc/stand/hpcboot/sh3/cpu/sh4.h
207
#define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI)
sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp
64
_reg_write_4(vaddr, dum);
sys/arch/landisk/landisk/machdep.c
395
_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
sys/arch/landisk/landisk/machdep.c
412
_reg_write_4(SH4_BCR4, BSC_BCR4_VAL);
sys/arch/landisk/landisk/machdep.c
422
_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
sys/arch/landisk/landisk/machdep.c
433
_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
sys/arch/landisk/landisk/machdep.c
436
_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
sys/arch/landisk/landisk/machdep.c
446
_reg_write_4(SH4_MCR, BSC_MCR_VAL);
sys/arch/landisk/stand/boot/delay.c
100
_reg_write_4(TCOR, 0xffffffff);
sys/arch/landisk/stand/boot/delay.c
101
_reg_write_4(TCNT, 0xffffffff);
sys/arch/mmeye/mmeye/machdep.c
456
_reg_write_4(SH4_BCR1, 0x0008000d);
sys/arch/mmeye/mmeye/machdep.c
458
_reg_write_4(SH4_WCR1, 0x11111111);
sys/arch/mmeye/mmeye/machdep.c
459
_reg_write_4(SH4_WCR2, 0xdd7845a7);
sys/arch/mmeye/mmeye/machdep.c
460
_reg_write_4(SH4_WCR3, 0x05555555);
sys/arch/mmeye/mmeye/machdep.c
461
_reg_write_4(SH4_MCR, 0x500921f4);
sys/arch/mmeye/mmeye/machdep.c
507
_reg_write_4(SH3_CCR, SH3_CCR_CE);
sys/arch/mmeye/mmeye/machdep.c
516
_reg_write_4(SH3_CCR, SH3_CCR_CE);
sys/arch/mmeye/mmeye/machdep.c
517
_reg_write_4(SH3_CCR, SH3_CCR_CF | SH3_CCR_CE); /* cache clear */
sys/arch/mmeye/mmeye/machdep.c
518
_reg_write_4(SH3_CCR, SH3_CCR_CE);
sys/arch/mmeye/stand/boot/wdvar.h
74
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/mmeye/stand/boot/wdvar.h
78
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/mmeye/stand/boot/wdvar.h
82
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/mmeye/stand/boot/wdvar.h
86
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/mmeye/stand/boot/wdvar.h
90
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/mmeye/stand/boot/wdvar.h
94
_reg_write_4(SH4_PTEA, _PG_PCMCIA_IO16 >> _PG_PCMCIA_SHIFT); \
sys/arch/playstation2/dev/sbus.c
169
_reg_write_4(SBUS_SMFLG_REG, SMFLG_PCMCIA_INT);
sys/arch/playstation2/dev/sbus.c
170
_reg_write_4(SBUS_SMFLG_REG, SMFLG_USB_INT);
sys/arch/playstation2/dev/sbus.c
226
_reg_write_4(SBUS_SMFLG_REG, SMFLG_PCMCIA_INT);
sys/arch/playstation2/dev/sbus.c
231
_reg_write_4(SBUS_SMFLG_REG, SMFLG_USB_INT);
sys/arch/playstation2/ee/dmac.c
100
_reg_write_4(D_STAT_REG, D_STAT_MEIM);
sys/arch/playstation2/ee/dmac.c
103
_reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK);
sys/arch/playstation2/ee/dmac.c
106
_reg_write_4(D_ENABLEW_REG, 0);
sys/arch/playstation2/ee/dmac.c
107
_reg_write_4(D_CTRL_REG, D_CTRL_DMAE);
sys/arch/playstation2/ee/dmac.c
132
_reg_write_4(D_STAT_REG, dispatch);
sys/arch/playstation2/ee/dmac.c
167
_reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask);
sys/arch/playstation2/ee/dmac.c
175
_reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch));
sys/arch/playstation2/ee/dmac.c
186
_reg_write_4(D_STAT_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) &
sys/arch/playstation2/ee/dmac.c
274
_reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
sys/arch/playstation2/ee/dmac.c
277
_reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR));
sys/arch/playstation2/ee/dmac.c
280
_reg_write_4(D_ENABLEW_REG, r & ~D_ENABLE_SUSPEND);
sys/arch/playstation2/ee/dmac.c
294
_reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
sys/arch/playstation2/ee/dmac.c
297
_reg_write_4(chcr, (_reg_read_4(chcr) & ~D_CHCR_STR));
sys/arch/playstation2/ee/dmac.c
300
_reg_write_4(D_ENABLEW_REG, r);
sys/arch/playstation2/ee/dmac.c
325
_reg_write_4(D_STAT_REG, D_STAT_CIS_BIT(ch));
sys/arch/playstation2/ee/dmac.c
327
_reg_write_4(D_PCR_REG, r | D_PCR_CPC_BIT(ch));
sys/arch/playstation2/ee/dmac.c
334
_reg_write_4(D_PCR_REG, _reg_read_4(D_PCR_REG) & ~D_PCR_CPC_BIT(ch))
sys/arch/playstation2/ee/dmac.c
374
_reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND);
sys/arch/playstation2/ee/dmac.c
377
_reg_write_4(D_CHCR_REG(__dmac_channel_base[ch]), v);
sys/arch/playstation2/ee/dmac.c
380
_reg_write_4(D_ENABLEW_REG, r);
sys/arch/playstation2/ee/dmac.c
88
_reg_write_4(D_ENABLEW_REG, D_ENABLE_SUSPEND);
sys/arch/playstation2/ee/dmac.c
98
_reg_write_4(D_STAT_REG, D_STAT_SIM);
sys/arch/playstation2/ee/gs.c
163
_reg_write_4(GIF_CTRL_REG, 1);
sys/arch/playstation2/ee/gsfb.c
360
_reg_write_4(D2_QWC_REG, 0);
sys/arch/playstation2/ee/gsfb.c
361
_reg_write_4(D2_MADR_REG, 0);
sys/arch/playstation2/ee/gsfb.c
362
_reg_write_4(D2_TADR_REG, 0);
sys/arch/playstation2/ee/gsfb.c
363
_reg_write_4(D2_CHCR_REG, 0);
sys/arch/playstation2/ee/gsfb.c
623
_reg_write_4(D2_MADR_REG, addr);
sys/arch/playstation2/ee/gsfb.c
625
_reg_write_4(D2_QWC_REG, bytetoqwc(size));
sys/arch/playstation2/ee/intc.c
103
_reg_write_4(I_STAT_REG, dispatch);
sys/arch/playstation2/ee/intc.c
136
_reg_write_4(I_MASK_REG, (_reg_read_4(I_MASK_REG) & mask) ^ mask);
sys/arch/playstation2/ee/intc.c
144
_reg_write_4(I_MASK_REG, _reg_read_4(I_MASK_REG) & (1 << ch));
sys/arch/playstation2/ee/intc.c
154
_reg_write_4(I_MASK_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) &
sys/arch/playstation2/ee/intc.c
78
_reg_write_4(I_STAT_REG, _reg_read_4(I_STAT_REG));
sys/arch/playstation2/ee/timer.c
103
_reg_write_4(T0_MODE_REG, _reg_read_4(T0_MODE_REG) | T_MODE_EQUF);
sys/arch/playstation2/ee/timer.c
117
_reg_write_4(T1_MODE_REG, T_MODE_EQUF | T_MODE_OVFF);
sys/arch/playstation2/ee/timer.c
130
_reg_write_4(T2_MODE_REG, T_MODE_EQUF | T_MODE_OVFF);
sys/arch/playstation2/ee/timer.c
142
_reg_write_4(T3_MODE_REG, T_MODE_EQUF | T_MODE_OVFF);
sys/arch/playstation2/ee/timer.c
69
_reg_write_4(T0_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
sys/arch/playstation2/ee/timer.c
70
_reg_write_4(T1_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
sys/arch/playstation2/ee/timer.c
71
_reg_write_4(T2_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
sys/arch/playstation2/ee/timer.c
72
_reg_write_4(T3_MODE_REG, (T_MODE_EQUF | T_MODE_OVFF));
sys/arch/playstation2/ee/timer.c
80
_reg_write_4(T0_COUNT_REG, 0);
sys/arch/playstation2/ee/timer.c
81
_reg_write_4(T0_COMP_REG, 5760);
sys/arch/playstation2/ee/timer.c
82
_reg_write_4(T0_MODE_REG, T_MODE_CLKS_BUSCLK256 | T_MODE_ZRET |
sys/arch/playstation2/ee/timer.c
91
_reg_write_4(T_COUNT_REG(timer), 0);
sys/arch/playstation2/ee/timer.c
92
_reg_write_4(T_COMP_REG(timer), 1);
sys/arch/playstation2/ee/timer.c
93
_reg_write_4(T_MODE_REG(timer), T_MODE_CUE | T_MODE_CMPE);
sys/arch/sh3/dev/shpcic.c
141
_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
sys/arch/sh3/dev/shpcic.c
144
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
sys/arch/sh3/dev/shpcic.c
146
_reg_write_4(SH4_PCICR, PCICR_BASE);
sys/arch/sh3/dev/shpcic.c
149
_reg_write_4(SH4_PCICONF2,
sys/arch/sh3/dev/shpcic.c
154
_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
sys/arch/sh3/dev/shpcic.c
156
_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
sys/arch/sh3/dev/shpcic.c
159
_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
sys/arch/sh3/dev/shpcic.c
161
_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
sys/arch/sh3/dev/shpcic.c
166
_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
sys/arch/sh3/dev/shpcic.c
168
_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
sys/arch/sh3/dev/shpcic.c
173
_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
sys/arch/sh3/dev/shpcic.c
175
_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
sys/arch/sh3/dev/shpcic.c
178
_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
sys/arch/sh3/dev/shpcic.c
180
_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
sys/arch/sh3/dev/shpcic.c
183
_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
sys/arch/sh3/dev/shpcic.c
185
_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
sys/arch/sh3/dev/shpcic.c
188
_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
sys/arch/sh3/dev/shpcic.c
190
_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
sys/arch/sh3/dev/shpcic.c
195
_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
sys/arch/sh3/dev/shpcic.c
196
_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
sys/arch/sh3/dev/shpcic.c
199
_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
sys/arch/sh3/dev/shpcic.c
200
_reg_write_4(SH4_PCILAR0, 0xac000000);
sys/arch/sh3/dev/shpcic.c
201
_reg_write_4(SH4_PCICONF5, 0xac000000);
sys/arch/sh3/dev/shpcic.c
204
_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
sys/arch/sh3/dev/shpcic.c
205
_reg_write_4(SH4_PCILAR1, 0xac000000);
sys/arch/sh3/dev/shpcic.c
206
_reg_write_4(SH4_PCICONF6, 0x8c000000);
sys/arch/sh3/dev/shpcic.c
209
_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
sys/arch/sh3/dev/shpcic.c
216
_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
sys/arch/sh3/dev/shpcic.c
296
_reg_write_4(SH4_PCIPAR, tag | reg);
sys/arch/sh3/dev/shpcic.c
298
_reg_write_4(SH4_PCIPAR, 0);
sys/arch/sh3/dev/shpcic.c
313
_reg_write_4(SH4_PCIPAR, tag | reg);
sys/arch/sh3/dev/shpcic.c
314
_reg_write_4(SH4_PCIPDR, data);
sys/arch/sh3/dev/shpcic.c
315
_reg_write_4(SH4_PCIPAR, 0);
sys/arch/sh3/sh3/cache_sh3.c
230
_reg_write_4(cca, va & CCA_TAGADDR_MASK);
sys/arch/sh3/sh3/cache_sh4.c
137
_reg_write_4(SH4_CCR, SH4_CCR_ICI|SH4_CCR_OCI);
sys/arch/sh3/sh3/cache_sh4.c
138
_reg_write_4(SH4_CCR, r);
sys/arch/sh3/sh3/cache_sh4.c
264
_reg_write_4(ccia, va & CCIA_TAGADDR_MASK); /* V = 0 */
sys/arch/sh3/sh3/clock.c
104
_reg_write_4(SH_(TCNT ## x), 0xffffffff); \
sys/arch/sh3/sh3/clock.c
255
_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
sys/arch/sh3/sh3/clock.c
256
_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
sys/arch/sh3/sh3/clock.c
268
_reg_write_4(SH_(TCOR1), 0xffffffff);
sys/arch/sh3/sh3/clock.c
274
_reg_write_4(SH_(TCOR2), 0xffffffff);
sys/arch/sh3/sh3/db_interface.c
499
_reg_write_4(SH3_CCR,
sys/arch/sh3/sh3/db_interface.c
540
_reg_write_4(SH4_CCR,
sys/arch/sh3/sh3/db_interface.c
573
_reg_write_4(SH4_CCR,
sys/arch/sh3/sh3/interrupt.c
460
_reg_write_4(iprreg, r);
sys/arch/sh3/sh3/interrupt.c
509
_reg_write_4(iprreg, bit);
sys/arch/sh3/sh3/interrupt.c
558
_reg_write_4(iprreg, bit);
sys/arch/sh3/sh3/interrupt.c
92
_reg_write_4(SH4_INTPRI00, 0);
sys/arch/sh3/sh3/interrupt.c
93
_reg_write_4(SH4_INTMSK00, INTMSK00_MASK_ALL);
sys/arch/sh3/sh3/mmu.c
111
_reg_write_4(SH_(PTEH), asid);
sys/arch/sh3/sh3/mmu_sh3.c
115
_reg_write_4(aa, 0);
sys/arch/sh3/sh3/mmu_sh3.c
194
_reg_write_4(SH3_MMUAA | a, newa);
sys/arch/sh3/sh3/mmu_sh3.c
195
_reg_write_4(SH3_MMUDA | a, newd);
sys/arch/sh3/sh3/mmu_sh3.c
53
_reg_write_4(SH3_MMUCR, SH3_MMUCR_TF | SH3_MMUCR_AT);
sys/arch/sh3/sh3/mmu_sh3.c
69
_reg_write_4(SH3_MMUAA | a, 0);
sys/arch/sh3/sh3/mmu_sh3.c
70
_reg_write_4(SH3_MMUDA | a, 0);
sys/arch/sh3/sh3/mmu_sh3.c
89
_reg_write_4(aa, 0);
sys/arch/sh3/sh3/mmu_sh4.c
101
_reg_write_4(SH4_PTEH, asid); /* set ASID for associative write */
sys/arch/sh3/sh3/mmu_sh4.c
104
_reg_write_4(SH4_PTEH, opteh); /* restore ASID */
sys/arch/sh3/sh3/mmu_sh4.c
118
_reg_write_4(addr, 0);
sys/arch/sh3/sh3/mmu_sh4.c
125
_reg_write_4(addr, 0);
sys/arch/sh3/sh3/mmu_sh4.c
155
_reg_write_4(SH4_UTLB_AA | (e << SH4_UTLB_E_SHIFT), 0);
sys/arch/sh3/sh3/mmu_sh4.c
156
_reg_write_4(SH4_UTLB_DA1 | (e << SH4_UTLB_E_SHIFT), 0);
sys/arch/sh3/sh3/mmu_sh4.c
160
_reg_write_4(SH4_ITLB_AA | (e << SH4_ITLB_E_SHIFT), 0);
sys/arch/sh3/sh3/mmu_sh4.c
161
_reg_write_4(SH4_ITLB_DA1 | (e << SH4_ITLB_E_SHIFT), 0);
sys/arch/sh3/sh3/mmu_sh4.c
208
_reg_write_4(SH4_PTEH, (va & ~PGOFSET) | asid);
sys/arch/sh3/sh3/mmu_sh4.c
213
_reg_write_4(SH4_PTEL, ptel);
sys/arch/sh3/sh3/mmu_sh4.c
215
_reg_write_4(SH4_PTEA,
sys/arch/sh3/sh3/mmu_sh4.c
218
_reg_write_4(SH4_PTEA, 0);
sys/arch/sh3/sh3/mmu_sh4.c
222
_reg_write_4(SH4_PTEH, opteh); /* restore old ASID */
sys/arch/sh3/sh3/mmu_sh4.c
55
_reg_write_4(SH4_MMUCR, 0); /* zero wired entry */
sys/arch/sh3/sh3/mmu_sh4.c
68
_reg_write_4(SH4_MMUCR, cr);
sys/arch/sh3/sh3/mmu_sh4.c
82
_reg_write_4(SH4_UTLB_AA | SH4_UTLB_A, va);
sys/arch/sh3/sh3/sh3_machdep.c
201
_reg_write_4(SH3_BRCR, (UBC_CTL_A_AFTER_INSN
sys/arch/sh3/sh3/sh3_machdep.c
205
_reg_write_4(SH3_BAMRA, 0x00000000);
sys/arch/sh3/sh3/sh3_machdep.c
558
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);