sys/arch/dreamcast/dreamcast/machdep.c

271

evtcode = _reg_read_4(SH4_INTEVT);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

148

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

76

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

95

KASSERT((_reg_read_4(SH4_PCTRA) & (1 << (pin * 2))) == 0); /*input*/

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

148

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

95

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

242

reg = _reg_read_4(SH4_WCR1);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

245

reg = _reg_read_4(SH4_WCR2);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

248

reg = _reg_read_4(SH4_WCR3);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

251

reg = _reg_read_4(SH4_PCR);

sys/arch/evbsh3/evbsh3/machdep.c

542

evtcode = _reg_read_4(SH3_INTEVT);

sys/arch/evbsh3/evbsh3/machdep.c

547

evtcode = _reg_read_4(SH7709_INTEVT2);

sys/arch/evbsh3/evbsh3/machdep.c

554

evtcode = _reg_read_4(SH4_INTEVT);

sys/arch/hpc/stand/hpcboot/sh3/cpu/7707.h

65

_reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \

sys/arch/hpc/stand/hpcboot/sh3/cpu/7709.h

54

_reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \

sys/arch/hpc/stand/hpcboot/sh3/cpu/7709a.h

54

_reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

284

r32 = _reg_read_4(tcnt);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh3_dev.cpp

287

r32 = _reg_read_4(tcor);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh4_dev.cpp

120

bitdisp(_reg_read_4(SH4_INTEVT));

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

108

r = _reg_read_4(SH3_CCR);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

118

r = _reg_read_4(SH4_CCR);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

161

r = _reg_read_4(SH3_MMUCR);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

181

r = _reg_read_4(SH3_MMUAA | a);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

185

r = _reg_read_4(SH3_MMUDA | a);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

200

r = _reg_read_4(SH4_MMUCR);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

217

r = _reg_read_4(SH4_ITLB_AA | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

222

r = _reg_read_4(SH4_ITLB_DA1 | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

230

r = _reg_read_4(SH4_ITLB_DA2 | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

239

r = _reg_read_4(SH4_UTLB_AA | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

245

r = _reg_read_4(SH4_UTLB_DA1 | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

255

r = _reg_read_4(SH4_UTLB_DA2 | e);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

56

asid = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

63

dum = _reg_read_4(vaddr);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

69

aae = _reg_read_4(SH3_MMUAA | entry_idx);

sys/arch/hpc/stand/hpcboot/sh3/sh_mmu.cpp

78

dae = _reg_read_4(SH3_MMUDA | entry_idx);

sys/arch/hpcsh/hpcsh/machdep.c

596

evtcode = _reg_read_4(CPU_IS_SH3 ? SH7709_INTEVT2 : SH4_INTEVT);

sys/arch/landisk/landisk/intr.c

82

evtcode = _reg_read_4(SH4_INTEVT);

sys/arch/landisk/stand/boot/delay.c

118

return ~(_reg_read_4(TCNT));

sys/arch/mmeye/mmeye/machdep.c

655

evtcode = _reg_read_4(SH_(INTEVT));

sys/arch/mmeye/stand/boot/clock.c

51

t1 = _reg_read_4(SH_(TCNT0));

sys/arch/mmeye/stand/boot/clock.c

53

t2 = _reg_read_4(SH_(TCNT0));

sys/arch/playstation2/dev/if_smap.c

355

*p++ = _reg_read_4(SMAP_RXFIFO_DATA_REG);

sys/arch/playstation2/dev/sbus.c

222

stat = _reg_read_4(SBUS_SMFLG_REG);

sys/arch/playstation2/ee/dmac.c

103

_reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK);

sys/arch/playstation2/ee/dmac.c

119

r = _reg_read_4(D_STAT_REG);

sys/arch/playstation2/ee/dmac.c

167

_reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask);

sys/arch/playstation2/ee/dmac.c

175

_reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch));

sys/arch/playstation2/ee/dmac.c

184

cur_mask = _reg_read_4(D_STAT_REG);

sys/arch/playstation2/ee/dmac.c

273

r = _reg_read_4(D_ENABLER_REG);

sys/arch/playstation2/ee/dmac.c

277

_reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR));

sys/arch/playstation2/ee/dmac.c

293

r = _reg_read_4(D_ENABLER_REG);

sys/arch/playstation2/ee/dmac.c

297

_reg_write_4(chcr, (_reg_read_4(chcr) & ~D_CHCR_STR));

sys/arch/playstation2/ee/dmac.c

321

r = _reg_read_4(D_PCR_REG);

sys/arch/playstation2/ee/dmac.c

334

_reg_write_4(D_PCR_REG, _reg_read_4(D_PCR_REG) & ~D_PCR_CPC_BIT(ch))

sys/arch/playstation2/ee/dmac.c

358

while (_reg_read_4(chcr) & D_CHCR_STR)

sys/arch/playstation2/ee/dmac.c

373

r = _reg_read_4(D_ENABLER_REG);

sys/arch/playstation2/ee/dmac.c

97

if (_reg_read_4(D_STAT_REG) & D_STAT_SIM)

sys/arch/playstation2/ee/dmac.c

99

if (_reg_read_4(D_STAT_REG) & D_STAT_MEIM)

sys/arch/playstation2/ee/gsfb.c

612

while (_reg_read_4(D2_QWC_REG))

sys/arch/playstation2/ee/intc.c

136

_reg_write_4(I_MASK_REG, (_reg_read_4(I_MASK_REG) & mask) ^ mask);

sys/arch/playstation2/ee/intc.c

144

_reg_write_4(I_MASK_REG, _reg_read_4(I_MASK_REG) & (1 << ch));

sys/arch/playstation2/ee/intc.c

152

cur_mask = _reg_read_4(I_MASK_REG);

sys/arch/playstation2/ee/intc.c

78

_reg_write_4(I_STAT_REG, _reg_read_4(I_STAT_REG));

sys/arch/playstation2/ee/intc.c

90

r = _reg_read_4(I_STAT_REG);

sys/arch/playstation2/ee/timer.c

103

_reg_write_4(T0_MODE_REG, _reg_read_4(T0_MODE_REG) | T_MODE_EQUF);

sys/arch/playstation2/playstation2/interrupt.c

279

(_reg_read_4(I_MASK_REG) << 16) |

sys/arch/playstation2/playstation2/interrupt.c

280

(_reg_read_4(I_STAT_REG) & 0x0000ffff),

sys/arch/playstation2/playstation2/interrupt.c

281

_reg_read_4(D_STAT_REG));

sys/arch/sh3/dev/shpcic.c

135

id = _reg_read_4(SH4_PCICONF0);

sys/arch/sh3/dev/shpcic.c

136

class = _reg_read_4(SH4_PCICONF2);

sys/arch/sh3/dev/shpcic.c

141

_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);

sys/arch/sh3/dev/shpcic.c

156

_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);

sys/arch/sh3/dev/shpcic.c

175

_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));

sys/arch/sh3/dev/shpcic.c

180

_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));

sys/arch/sh3/dev/shpcic.c

185

_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));

sys/arch/sh3/dev/shpcic.c

190

_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));

sys/arch/sh3/dev/shpcic.c

297

data = _reg_read_4(SH4_PCIPDR);

sys/arch/sh3/dev/shpcic.c

98

id = _reg_read_4(SH4_PCICONF0);

sys/arch/sh3/sh3/cache_sh3.c

86

r = _reg_read_4(SH3_CCR);

sys/arch/sh3/sh3/cache_sh4.c

141

r = _reg_read_4(SH4_CCR);

sys/arch/sh3/sh3/clock.c

109

(0xffffffff - _reg_read_4(SH_(TCNT ## x)))

sys/arch/sh3/sh3/clock.c

213

return 0xffffffff - _reg_read_4(SH_(TCNT2));

sys/arch/sh3/sh3/db_interface.c

282

r = _reg_read_4(SH3_MMUCR);

sys/arch/sh3/sh3/db_interface.c

287

i = _reg_read_4(SH3_PTEH) & SH3_PTEH_ASID_MASK;

sys/arch/sh3/sh3/db_interface.c

299

r = _reg_read_4(SH3_MMUAA | a);

sys/arch/sh3/sh3/db_interface.c

312

r = _reg_read_4(SH3_MMUDA | a);

sys/arch/sh3/sh3/db_interface.c

338

r = _reg_read_4(SH4_MMUCR);

sys/arch/sh3/sh3/db_interface.c

345

i = _reg_read_4(SH4_PTEH) & SH4_PTEH_ASID_MASK;

sys/arch/sh3/sh3/db_interface.c

410

*paa = _reg_read_4(SH4_ITLB_AA | e);

sys/arch/sh3/sh3/db_interface.c

411

*pda1 = _reg_read_4(SH4_ITLB_DA1 | e);

sys/arch/sh3/sh3/db_interface.c

412

*pda2 = _reg_read_4(SH4_ITLB_DA2 | e);

sys/arch/sh3/sh3/db_interface.c

420

*paa = _reg_read_4(SH4_UTLB_AA | e);

sys/arch/sh3/sh3/db_interface.c

421

*pda1 = _reg_read_4(SH4_UTLB_DA1 | e);

sys/arch/sh3/sh3/db_interface.c

422

*pda2 = _reg_read_4(SH4_UTLB_DA2 | e);

sys/arch/sh3/sh3/db_interface.c

500

_reg_read_4(SH3_CCR) & ~SH3_CCR_CE);

sys/arch/sh3/sh3/db_interface.c

519

r = _reg_read_4(cca | (way << sh_cache_way_shift));

sys/arch/sh3/sh3/db_interface.c

541

_reg_read_4(SH4_CCR) & ~(SH4_CCR_ICE | SH4_CCR_OCE));

sys/arch/sh3/sh3/db_interface.c

556

r = _reg_read_4(SH4_CCIA | (i << CCIA_ENTRY_SHIFT));

sys/arch/sh3/sh3/db_interface.c

566

r = _reg_read_4(SH4_CCDA | e);

sys/arch/sh3/sh3/db_interface.c

574

_reg_read_4(SH4_CCR) | SH4_CCR_ICE | SH4_CCR_OCE);

sys/arch/sh3/sh3/exception.c

158

trapcode = _reg_read_4(SH_(TRA)) >> 2;

sys/arch/sh3/sh3/interrupt.c

391

printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));

sys/arch/sh3/sh3/interrupt.c

395

printf(" INTEVT2=0x%x", _reg_read_4(SH7709_INTEVT2));

sys/arch/sh3/sh3/interrupt.c

458

r = _reg_read_4(iprreg);

sys/arch/sh3/sh3/mmu.c

84

r = _reg_read_4(SH3_MMUCR);

sys/arch/sh3/sh3/mmu.c

95

r = _reg_read_4(SH4_MMUCR);

sys/arch/sh3/sh3/mmu_sh3.c

111

entry = _reg_read_4(aa)

sys/arch/sh3/sh3/mmu_sh3.c

173

entry = _reg_read_4(SH3_MMUAA | a);

sys/arch/sh3/sh3/mmu_sh3.c

88

if ((_reg_read_4(aa) & SH3_MMUAA_D_ASID_MASK) == asid)

sys/arch/sh3/sh3/mmu_sh4.c

116

uint32_t aa = _reg_read_4(addr);

sys/arch/sh3/sh3/mmu_sh4.c

123

uint32_t aa = _reg_read_4(addr);

sys/arch/sh3/sh3/mmu_sh4.c

178

limit = _reg_read_4(SH4_MMUCR) & SH4_MMUCR_URB_MASK;

sys/arch/sh3/sh3/mmu_sh4.c

202

opteh = _reg_read_4(SH4_PTEH); /* save old ASID */

sys/arch/sh3/sh3/mmu_sh4.c

99

opteh = _reg_read_4(SH4_PTEH); /* save current ASID */

sys/arch/sh3/sh3/pmb.c

106

uint32_t addr = _reg_read_4(ST40_PMB_AA + offset);

sys/arch/sh3/sh3/pmb.c

111

uint32_t data = _reg_read_4(ST40_PMB_DA + offset);

sys/arch/sh3/sh3/pmb.c

55

pascr = _reg_read_4(ST40_PASCR);

sys/arch/sh3/sh3/pmb.c

67

uint32_t mmucr = _reg_read_4(SH4_MMUCR);