_emac3_reg_write_4
_emac3_reg_write_4(EMAC3_MR1, r);
_emac3_reg_write_4(EMAC3_MR1, sc->mode1_reg);
_emac3_reg_write_4(EMAC3_MR0, MR0_TXE | MR0_RXE);
_emac3_reg_write_4(EMAC3_MR0,
_emac3_reg_write_4(EMAC3_ISER, ~0);
_emac3_reg_write_4(EMAC3_ISER, 0);
_emac3_reg_write_4(EMAC3_ISR, _emac3_reg_read_4(EMAC3_ISR));
_emac3_reg_write_4(EMAC3_ISR, r);
_emac3_reg_write_4(EMAC3_TMR0, TMR0_GNP0);
_emac3_reg_write_4(EMAC3_RMR, r);
_emac3_reg_write_4(EMAC3_RMR, r);
_emac3_reg_write_4(EMAC3_MR0, MR0_SRST);
_emac3_reg_write_4(EMAC3_IAHR, (eaddr[0] << 8) | eaddr[1]);
_emac3_reg_write_4(EMAC3_IALR, (eaddr[2] << 24) | (eaddr[3] << 16) |
_emac3_reg_write_4(EMAC3_IPGVR, 4);
_emac3_reg_write_4(EMAC3_RMR,
_emac3_reg_write_4(EMAC3_TMR1,
_emac3_reg_write_4(EMAC3_TRTR,
_emac3_reg_write_4(EMAC3_RWMR,
_emac3_reg_write_4(EMAC3_STACR, STACR_WRITE |
_emac3_reg_write_4(EMAC3_STACR, STACR_READ |
_emac3_reg_write_4(EMAC3_MR1, r);