sys/arch/powerpc/booke/dev/pq3gpio.c
477
{ __PPCBIT(2), __PPCBITS( 2, 3), 0 }, /* GPIO_2 */
sys/arch/powerpc/booke/dev/pq3gpio.c
484
{ __PPCBIT(3), __PPCBITS(18,19), 0 }, /* GPIO_9 */
sys/arch/powerpc/include/booke/e500reg.h
100
#define CATTR_VLD __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
140
#define PEX_CONFIG_ADDR_EN __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
160
#define PEXOWAR_EN __PPCBIT(0) /* enable window */
sys/arch/powerpc/include/booke/e500reg.h
161
#define PEXOWAR_ROE __PPCBIT(3) /* relaxed ordering enable */
sys/arch/powerpc/include/booke/e500reg.h
162
#define PEXOWAR_NS __PPCBIT(4) /* no snoop enable */
sys/arch/powerpc/include/booke/e500reg.h
183
#define PEXIWAR_EN __PPCBIT(0) /* enable window */
sys/arch/powerpc/include/booke/e500reg.h
184
#define PEXIWAR_PF __PPCBIT(3) /* prefetchable */
sys/arch/powerpc/include/booke/e500reg.h
252
#define PEXERRDR_ICCA __PPCBIT(14)
sys/arch/powerpc/include/booke/e500reg.h
279
#define L2CTL_L2E __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
280
#define L2CTL_L2I __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
283
#define L2CTL_L2DO __PPCBIT(9)
sys/arch/powerpc/include/booke/e500reg.h
284
#define L2CTL_L2IO __PPCBIT(10)
sys/arch/powerpc/include/booke/e500reg.h
285
#define L2CTL_L2INTDIS __PPCBIT(12)
sys/arch/powerpc/include/booke/e500reg.h
287
#define L2CTL_L2LO __PPCBIT(18)
sys/arch/powerpc/include/booke/e500reg.h
288
#define L2CTL_L2SLC __PPCBIT(19)
sys/arch/powerpc/include/booke/e500reg.h
289
#define L2CTL_L2LFR __PPCBIT(21)
sys/arch/powerpc/include/booke/e500reg.h
291
#define L2CTL_L2STASHDIS __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
318
#define SPMODE_EN __PPCBIT(0) /* Enable eSPI: 0=disabled, 1=enabled */
sys/arch/powerpc/include/booke/e500reg.h
319
#define SPMODE_LOOP __PPCBIT(1) /* Loop mode: 0=normal, 1=loopback */
sys/arch/powerpc/include/booke/e500reg.h
320
#define SPMODE_OD __PPCBIT(2) /* P1023: Open drain mode: 0=actively driven, 1=open drain */
sys/arch/powerpc/include/booke/e500reg.h
327
#define SPIE_TXE __PPCBIT(16) /* Tx FIFO is empty */
sys/arch/powerpc/include/booke/e500reg.h
328
#define SPIE_DON __PPCBIT(17) /* Last character was transmitted */
sys/arch/powerpc/include/booke/e500reg.h
329
#define SPIE_RXT __PPCBIT(18) /* Rx FIFO has more than RXTHR bytes */
sys/arch/powerpc/include/booke/e500reg.h
330
#define SPIE_RXF __PPCBIT(19) /* Rx FIFO is full */
sys/arch/powerpc/include/booke/e500reg.h
331
#define SPIE_TXT __PPCBIT(20) /* Tx FIFO has less than TXTHR bytes */
sys/arch/powerpc/include/booke/e500reg.h
332
#define SPIE_RNE __PPCBIT(22) /* Not empty: 0=empty, 1=not empty */
sys/arch/powerpc/include/booke/e500reg.h
333
#define SPIE_TNF __PPCBIT(23) /* Tx FIFO not full: 0=full, 1=not full */
sys/arch/powerpc/include/booke/e500reg.h
335
#define SPIM_TXE __PPCBIT(16)
sys/arch/powerpc/include/booke/e500reg.h
336
#define SPIM_DON __PPCBIT(17)
sys/arch/powerpc/include/booke/e500reg.h
337
#define SPIM_RXT __PPCBIT(18)
sys/arch/powerpc/include/booke/e500reg.h
338
#define SPIM_RXF __PPCBIT(19)
sys/arch/powerpc/include/booke/e500reg.h
339
#define SPIM_TXT __PPCBIT(20)
sys/arch/powerpc/include/booke/e500reg.h
340
#define SPIM_RNE __PPCBIT(22)
sys/arch/powerpc/include/booke/e500reg.h
341
#define SPIM_TNF __PPCBIT(23)
sys/arch/powerpc/include/booke/e500reg.h
344
#define SPCOM_RXDELAY __PPCBIT(2) /* 0=normal eSPI operation */
sys/arch/powerpc/include/booke/e500reg.h
345
#define SPCOM_DO __PPCBIT(3) /* 0=normal eSPI operation, 1=Winbond dual output read */
sys/arch/powerpc/include/booke/e500reg.h
346
#define SPCOM_TO __PPCBIT(4) /* Transmit only: 0=normal operation, 1=No reception is done for the frame */
sys/arch/powerpc/include/booke/e500reg.h
347
#define SPCOM_HLD __PPCBIT(5) /* 0=normal operation, 1=Mask first generated SPI_CLK */
sys/arch/powerpc/include/booke/e500reg.h
348
#define SPCOM_LS __PPCBIT(6) /* P1023: Late sample: 0=normal operation, 1=Late data sample */
sys/arch/powerpc/include/booke/e500reg.h
358
#define SPMODEn_CI __PPCBIT(0) /* Clock invert: 0=inactive state of SPI_CLK is low, 1=high */
sys/arch/powerpc/include/booke/e500reg.h
359
#define SPMODEn_CP __PPCBIT(1) /* Clock phase: SPI_CLK starts toggling at the middle of the data transfer, 1=beginning */
sys/arch/powerpc/include/booke/e500reg.h
360
#define SPMODEn_REV __PPCBIT(2) /* Reverse data mode: 0=LSB of the character sent and received first, 1=MSB */
sys/arch/powerpc/include/booke/e500reg.h
361
#define SPMODEn_DIV16 __PPCBIT(3) /* Divide by 16: 0=System clock, 1=System clock/16 */
sys/arch/powerpc/include/booke/e500reg.h
363
#define SPMODEn_ODD __PPCBIT(8) /* 0=Even division, 1=Odd division */
sys/arch/powerpc/include/booke/e500reg.h
364
#define SPMODEn_POL __PPCBIT(11) /* CS polarity: 0=Asserted high/Negated low, 1=Asserted low/Negated high */
sys/arch/powerpc/include/booke/e500reg.h
381
#define USB_EN __PPCBIT(29)
sys/arch/powerpc/include/booke/e500reg.h
382
#define USB_ULPI_INT_EN __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
406
#define DCR_SNOOP __PPCBIT(25) /* DMA transactions are snooped */
sys/arch/powerpc/include/booke/e500reg.h
407
#define DCR_RD_SAFE __PPCBIT(29) /* memory is read safe */
sys/arch/powerpc/include/booke/e500reg.h
408
#define DCR_RD_PFE __PPCBIT(30) /* memory is prefetch safe */
sys/arch/powerpc/include/booke/e500reg.h
409
#define DCR_RD_PF_SIZE __PPCBIT(31) /* prefetch size is 32-bytes */
sys/arch/powerpc/include/booke/e500reg.h
424
#define PCI1_CLK_SEL __PPCBIT(16)
sys/arch/powerpc/include/booke/e500reg.h
425
#define PCI2_CLK_SEL __PPCBIT(17)
sys/arch/powerpc/include/booke/e500reg.h
442
#define PORDEVSR_ECW1 __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
443
#define PORDEVSR_ECW2 __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
444
#define PORDEVSR_SGMII1_DIS1 __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
445
#define PORDEVSR_SGMII1_DIS2 __PPCBIT(3)
sys/arch/powerpc/include/booke/e500reg.h
446
#define PORDEVSR_SGMII1_DIS3 __PPCBIT(4)
sys/arch/powerpc/include/booke/e500reg.h
447
#define PORDEVSR_SGMII1_DIS4 __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
449
#define PORDEVSR_PCI1 __PPCBIT(8)
sys/arch/powerpc/include/booke/e500reg.h
49
#define BPTR_EN __PPCBIT(0) /* Boot Page Enabled */
sys/arch/powerpc/include/booke/e500reg.h
496
#define PORDEVSR_PCI2_ARB __PPCBIT(13)
sys/arch/powerpc/include/booke/e500reg.h
497
#define PORDEVSR_PCI1_ARB __PPCBIT(14)
sys/arch/powerpc/include/booke/e500reg.h
498
#define PORDEVSR_PCI32 __PPCBIT(15)
sys/arch/powerpc/include/booke/e500reg.h
501
#define PORDEVSR_PCI1_SPD __PPCBIT(16)
sys/arch/powerpc/include/booke/e500reg.h
502
#define PORDEVSR_PCI2_SPD __PPCBIT(17)
sys/arch/powerpc/include/booke/e500reg.h
503
#define PORDEVSR_SYS_SPD __PPCBIT(17) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
504
#define PORDEVSR_CORE_SPD __PPCBIT(18) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
508
#define PORDEVSR_FEC_DIS __PPCBIT(24)
sys/arch/powerpc/include/booke/e500reg.h
509
#define PORDEVSR_RTPE __PPCBIT(25)
sys/arch/powerpc/include/booke/e500reg.h
510
#define PORDEVSR_RIO_CTLS __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
518
#define GPIOCR_TX2 __PPCBIT(6) /* Enable TSEC2_TX[7:0] as GP output */
sys/arch/powerpc/include/booke/e500reg.h
519
#define GPIOCR_RX2 __PPCBIT(7) /* Enable TSEC2_RX[7:0] as GP input */
sys/arch/powerpc/include/booke/e500reg.h
520
#define GPIOCR_PCIOUT __PPCBIT(14) /* Enable PCI2_AD[15:8] as GP output */
sys/arch/powerpc/include/booke/e500reg.h
521
#define GPIOCR_PCIIN __PPCBIT(15) /* Enable PCI2_AD[7:0] as GP input */
sys/arch/powerpc/include/booke/e500reg.h
522
#define GPIOCR_GPOUT __PPCBIT(22) /* Enable GPOUT[24:31] as GP output */
sys/arch/powerpc/include/booke/e500reg.h
532
#define PMUXCR_SD_DATA __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
533
#define PMUXCR_SDHC_CD __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
534
#define PMUXCR_SDHC_WP __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
535
#define PMUXCR_PCI_REQGNT3 __PPCBIT(3)
sys/arch/powerpc/include/booke/e500reg.h
536
#define PMUXCR_TSEC1_TS __PPCBIT(3)
sys/arch/powerpc/include/booke/e500reg.h
537
#define PMUXCR_PCI_REQGNT4 __PPCBIT(4)
sys/arch/powerpc/include/booke/e500reg.h
538
#define PMUXCR_TSEC2_TS __PPCBIT(4)
sys/arch/powerpc/include/booke/e500reg.h
539
#define PMUXCR_USB1 __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
540
#define PMUXCR_TSEC3_TS __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
541
#define PMUXCR_USB2 __PPCBIT(6)
sys/arch/powerpc/include/booke/e500reg.h
543
#define PMUXCR_USB __PPCBIT(6)
sys/arch/powerpc/include/booke/e500reg.h
544
#define PMUXCR_TSEC1 __PPCBIT(14)
sys/arch/powerpc/include/booke/e500reg.h
545
#define PMUXCR_DMA0 __PPCBIT(14)
sys/arch/powerpc/include/booke/e500reg.h
546
#define PMUXCR_DMA2 __PPCBIT(15)
sys/arch/powerpc/include/booke/e500reg.h
547
#define PMUXCR_QE0 __PPCBIT(16)
sys/arch/powerpc/include/booke/e500reg.h
548
#define PMUXCR_QE1 __PPCBIT(17)
sys/arch/powerpc/include/booke/e500reg.h
549
#define PMUXCR_QE2 __PPCBIT(18)
sys/arch/powerpc/include/booke/e500reg.h
550
#define PMUXCR_QE3 __PPCBIT(19)
sys/arch/powerpc/include/booke/e500reg.h
551
#define PMUXCR_QE8 __PPCBIT(24)
sys/arch/powerpc/include/booke/e500reg.h
552
#define PMUXCR_QE9 __PPCBIT(25)
sys/arch/powerpc/include/booke/e500reg.h
553
#define PMUXCR_QE10 __PPCBIT(26)
sys/arch/powerpc/include/booke/e500reg.h
554
#define PMUXCR_QE11 __PPCBIT(27)
sys/arch/powerpc/include/booke/e500reg.h
555
#define PMUXCR_QE12 __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
556
#define PMUXCR_DMA1 __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
557
#define PMUXCR_DMA3 __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
563
#define DEVDISR_PCI1 __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
564
#define DEVDISR_QMAN_BMAN __PPCBIT(0) /* P1023 */
sys/arch/powerpc/include/booke/e500reg.h
565
#define DEVDISR_PCI2 __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
566
#define DEVDISR_FMAN __PPCBIT(1) /* P1023 */
sys/arch/powerpc/include/booke/e500reg.h
567
#define DEVDISR_PCIE __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
568
#define DEVDISR_MACSEC __PPCBIT(3) /* P1023 */
sys/arch/powerpc/include/booke/e500reg.h
569
#define DEVDISR_LBC __PPCBIT(4)
sys/arch/powerpc/include/booke/e500reg.h
570
#define DEVDISR_PCIE2 __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
571
#define DEVDISR_PCIE3 __PPCBIT(6)
sys/arch/powerpc/include/booke/e500reg.h
572
#define DEVDISR_SEC __PPCBIT(7)
sys/arch/powerpc/include/booke/e500reg.h
573
#define DEVDISR_PME __PPCBIT(8)
sys/arch/powerpc/include/booke/e500reg.h
574
#define DEVDISR_USB1 __PPCBIT(8) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
575
#define DEVDISR_TLU1 __PPCBIT(9)
sys/arch/powerpc/include/booke/e500reg.h
576
#define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
577
#define DEVDISR_TLU2 __PPCBIT(10)
sys/arch/powerpc/include/booke/e500reg.h
578
#define DEVDISR_ESDHC_10 __PPCBIT(10)
sys/arch/powerpc/include/booke/e500reg.h
579
#define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
580
#define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
581
#define DEVDISR_SRIO __PPCBIT(12)
sys/arch/powerpc/include/booke/e500reg.h
582
#define DEVDISR_ESDHC_12 __PPCBIT(12) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
583
#define DEVDISR_RMSG __PPCBIT(13)
sys/arch/powerpc/include/booke/e500reg.h
584
#define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
585
#define DEVDISR_DDR2_14 __PPCBIT(14)
sys/arch/powerpc/include/booke/e500reg.h
586
#define DEVDISR_DDR_15 __PPCBIT(15)
sys/arch/powerpc/include/booke/e500reg.h
587
#define DEVDISR_SPI_15 __PPCBIT(15) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
588
#define DEVDISR_E500 __PPCBIT(16)
sys/arch/powerpc/include/booke/e500reg.h
589
#define DEVDISR_DDR_16 __PPCBIT(16) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
590
#define DEVDISR_TB __PPCBIT(17)
sys/arch/powerpc/include/booke/e500reg.h
591
#define DEVDISR_E500_1 __PPCBIT(18)
sys/arch/powerpc/include/booke/e500reg.h
592
#define DEVDISR_TB_1 __PPCBIT(19)
sys/arch/powerpc/include/booke/e500reg.h
593
#define DEVDISR_SATA2 __PPCBIT(20) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
594
#define DEVDISR_DMA __PPCBIT(21)
sys/arch/powerpc/include/booke/e500reg.h
595
#define DEVDISR_DMA2 __PPCBIT(22)
sys/arch/powerpc/include/booke/e500reg.h
596
#define DEVDISR_SRDS2 __PPCBIT(22) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
597
#define DEVDISR_TSEC1 __PPCBIT(24)
sys/arch/powerpc/include/booke/e500reg.h
598
#define DEVDISR_TSEC2 __PPCBIT(25)
sys/arch/powerpc/include/booke/e500reg.h
599
#define DEVDISR_TSEC3 __PPCBIT(26)
sys/arch/powerpc/include/booke/e500reg.h
600
#define DEVDISR_TSEC4 __PPCBIT(27)
sys/arch/powerpc/include/booke/e500reg.h
601
#define DEVDISR_FEC __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
602
#define DEVDISR_SPI_28 __PPCBIT(28) /* P2020 */
sys/arch/powerpc/include/booke/e500reg.h
603
#define DEVDISR_I2C __PPCBIT(29)
sys/arch/powerpc/include/booke/e500reg.h
604
#define DEVDISR_DUART __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
605
#define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */
sys/arch/powerpc/include/booke/e500reg.h
639
#define HRESET_REQ __PPCBIT(30) /* hardware reset request */
sys/arch/powerpc/include/booke/e500reg.h
65
#define CS_CONFIG_EN __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
668
#define BR_WP __PPCBIT(23)
sys/arch/powerpc/include/booke/e500reg.h
68
#define SDRAM_CFG_MEM_EN __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
680
#define BR_V __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
684
#define OR_BCTLD __PPCBIT(19)
sys/arch/powerpc/include/booke/e500reg.h
685
#define OR_CSNT __PPCBIT(20)
sys/arch/powerpc/include/booke/e500reg.h
687
#define OR_XACS __PPCBIT(23)
sys/arch/powerpc/include/booke/e500reg.h
689
#define OR_SETA __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
69
#define SDRAM_CFG_SREN __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
690
#define OR_TRLX __PPCBIT(29)
sys/arch/powerpc/include/booke/e500reg.h
691
#define OR_EHTR __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
692
#define OR_EAD __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
70
#define SDRAM_CFG_ECC_EN __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
71
#define SDRAM_CFG_RDEN __PPCBIT(3)
sys/arch/powerpc/include/booke/e500reg.h
727
#define LTESR_BM __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
728
#define LTESR_FCT __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
729
#define LTESR_PAR __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
730
#define LTESR_WP __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
731
#define LTESR_ATMW __PPCBIT(8)
sys/arch/powerpc/include/booke/e500reg.h
732
#define LTESR_ATMR __PPCBIT(9)
sys/arch/powerpc/include/booke/e500reg.h
733
#define LTESR_CS __PPCBIT(12)
sys/arch/powerpc/include/booke/e500reg.h
734
#define LTESR_UCC __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
735
#define LTESR_CC __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
737
#define LTEDR_BMD __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
738
#define LTEDR_FCTD __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
739
#define LTEDR_PARD __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
740
#define LTEDR_WPD __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
741
#define LTEDR_WARA __PPCBIT(8)
sys/arch/powerpc/include/booke/e500reg.h
742
#define LTEDR_RAWA __PPCBIT(9)
sys/arch/powerpc/include/booke/e500reg.h
743
#define LTEDR_CSD __PPCBIT(12)
sys/arch/powerpc/include/booke/e500reg.h
744
#define LTEDR_UCCD __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
745
#define LTEDR_CCD __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
747
#define LTEIR_BMI __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
748
#define LTEIR_FCTI __PPCBIT(1)
sys/arch/powerpc/include/booke/e500reg.h
749
#define LTEIR_PARI __PPCBIT(2)
sys/arch/powerpc/include/booke/e500reg.h
75
#define SDRAM_CFG_DYN_PWR __PPCBIT(10)
sys/arch/powerpc/include/booke/e500reg.h
750
#define LTEIR_WPI __PPCBIT(5)
sys/arch/powerpc/include/booke/e500reg.h
751
#define LTEIR_WARA __PPCBIT(8)
sys/arch/powerpc/include/booke/e500reg.h
752
#define LTEIR_RAWA __PPCBIT(9)
sys/arch/powerpc/include/booke/e500reg.h
753
#define LTEIR_CSI __PPCBIT(12)
sys/arch/powerpc/include/booke/e500reg.h
754
#define LTEIR_UCCI __PPCBIT(30)
sys/arch/powerpc/include/booke/e500reg.h
755
#define LTEIR_CCI __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
757
#define LTEATR_RWB __PPCBIT(3)
sys/arch/powerpc/include/booke/e500reg.h
761
#define LTEATR_V __PPCBIT(31)
sys/arch/powerpc/include/booke/e500reg.h
771
#define FMR_BOOT __PPCBIT(20)
sys/arch/powerpc/include/booke/e500reg.h
772
#define FMR_ECCM __PPCBIT(23)
sys/arch/powerpc/include/booke/e500reg.h
809
#define FPAR_S_MS __PPCBIT(22) /* Main(0)/Spare(1) */
sys/arch/powerpc/include/booke/e500reg.h
812
#define FPAR_L_MS __PPCBIT(20) /* Main(0)/Spare(1) */
sys/arch/powerpc/include/booke/e500reg.h
817
#define FECC_V __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
818
#define FECC_ECC __PPCBIT(8,31)
sys/arch/powerpc/include/booke/e500reg.h
823
#define MXMR_RFEN __PPCBIT(1) /* Refresh enable */
sys/arch/powerpc/include/booke/e500reg.h
829
#define MXMR_UWPL __PPCBIT(3) /* LUPWAIT is active low */
sys/arch/powerpc/include/booke/e500reg.h
845
#define MXMR_GPL4 __PPCBIT(13) /* LGPL4 output line disable */
sys/arch/powerpc/include/booke/e500reg.h
88
#define ERR_MMEE __PPCBIT(0)
sys/arch/powerpc/include/booke/e500reg.h
89
#define ERR_APEE __PPCBIT(23)
sys/arch/powerpc/include/booke/e500reg.h
90
#define ERR_ACEE __PPCBIT(24)
sys/arch/powerpc/include/booke/e500reg.h
91
#define ERR_MBEE __PPCBIT(28)
sys/arch/powerpc/include/booke/e500reg.h
92
#define ERR_SBEE __PPCBIT(29)
sys/arch/powerpc/include/booke/e500reg.h
93
#define ERR_MSEE __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
128
#define IEVENT_BABR __PPCBIT(0) /* babbling receive error */
sys/arch/powerpc/include/booke/etsecreg.h
129
#define IEVENT_RXC __PPCBIT(1) /* receive control interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
130
#define IEVENT_BSY __PPCBIT(2) /* busy condition interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
131
#define IEVENT_EBERR __PPCBIT(3) /* internal bus error */
sys/arch/powerpc/include/booke/etsecreg.h
132
#define IEVENT_MSR0 __PPCBIT(5) /* MIB counter overflow */
sys/arch/powerpc/include/booke/etsecreg.h
133
#define IEVENT_GTSC __PPCBIT(6) /* graceful transmit stop complete */
sys/arch/powerpc/include/booke/etsecreg.h
134
#define IEVENT_BABT __PPCBIT(7) /* babbing transmit error */
sys/arch/powerpc/include/booke/etsecreg.h
135
#define IEVENT_TXC __PPCBIT(8) /* transmit control interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
136
#define IEVENT_TXE __PPCBIT(9) /* transmit error */
sys/arch/powerpc/include/booke/etsecreg.h
137
#define IEVENT_TXB __PPCBIT(10) /* transmit buffer */
sys/arch/powerpc/include/booke/etsecreg.h
138
#define IEVENT_TXF __PPCBIT(11) /* transmit frame interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
139
#define IEVENT_LC __PPCBIT(13) /* late collision */
sys/arch/powerpc/include/booke/etsecreg.h
140
#define IEVENT_CRL __PPCBIT(14) /* collision retry limit */
sys/arch/powerpc/include/booke/etsecreg.h
141
#define IEVENT_XFUN __PPCBIT(15) /* transmit fifo underrun */
sys/arch/powerpc/include/booke/etsecreg.h
142
#define IEVENT_RXB __PPCBIT(16) /* receive buffer */
sys/arch/powerpc/include/booke/etsecreg.h
143
#define IEVENT_TWK __PPCBIT(19) /* timer wakeup */
sys/arch/powerpc/include/booke/etsecreg.h
144
#define IEVENT_MAG __PPCBIT(20) /* magic packet detected */
sys/arch/powerpc/include/booke/etsecreg.h
145
#define IEVENT_MMRD __PPCBIT(21) /* MMI management read complete */
sys/arch/powerpc/include/booke/etsecreg.h
146
#define IEVENT_MMWR __PPCBIT(22) /* MMI management write complete */
sys/arch/powerpc/include/booke/etsecreg.h
147
#define IEVENT_GRSC __PPCBIT(23) /* graceful receive stop complete */
sys/arch/powerpc/include/booke/etsecreg.h
148
#define IEVENT_RXF __PPCBIT(24) /* receive frame interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
149
#define IEVENT_FGPI __PPCBIT(27) /* filer generated general purpose interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
150
#define IEVENT_FIR __PPCBIT(28) /* receive queue filer is invalid */
sys/arch/powerpc/include/booke/etsecreg.h
151
#define IEVENT_FIQ __PPCBIT(29) /* filed frame to invalid receive queue */
sys/arch/powerpc/include/booke/etsecreg.h
152
#define IEVENT_DPE __PPCBIT(30) /* internal data parity error */
sys/arch/powerpc/include/booke/etsecreg.h
153
#define IEVENT_PERR __PPCBIT(31) /* Receive parse error for TOE */
sys/arch/powerpc/include/booke/etsecreg.h
158
#define ECNTRL_FIFM __PPCBIT(16) /* FIFO mode enable */
sys/arch/powerpc/include/booke/etsecreg.h
159
#define ECNTRL_CLRCNT __PPCBIT(17) /* Clear all MIB counters */
sys/arch/powerpc/include/booke/etsecreg.h
160
#define ECNTRL_AUTOZ __PPCBIT(18) /* Auto zero MIB counter on read */
sys/arch/powerpc/include/booke/etsecreg.h
161
#define ECNTRL_STEN __PPCBIT(19) /* MIB Statistics Enabled */
sys/arch/powerpc/include/booke/etsecreg.h
162
#define ECNTRL_GMIIM __PPCBIT(25) /* GMII Interface Mode */
sys/arch/powerpc/include/booke/etsecreg.h
163
#define ECNTRL_TBIM __PPCBIT(26) /* Ten-Bit Interface Mode */
sys/arch/powerpc/include/booke/etsecreg.h
164
#define ECNTRL_RPM __PPCBIT(27) /* Reduced Pin Mode */
sys/arch/powerpc/include/booke/etsecreg.h
165
#define ECNTRL_R100M __PPCBIT(28) /* RGMII/RMII 100 Mode */
sys/arch/powerpc/include/booke/etsecreg.h
166
#define ECNTRL_RMM __PPCBIT(29) /* Reduced Pin Mode for 10/100 */
sys/arch/powerpc/include/booke/etsecreg.h
167
#define ECNTRL_SGMIIM __PPCBIT(30) /* SGMII Interface Mode */
sys/arch/powerpc/include/booke/etsecreg.h
172
#define DMACTRL_LE __PPCBIT(16) /* Little Endian Descriptor Mode */
sys/arch/powerpc/include/booke/etsecreg.h
173
#define DMACTRL_TDSEN __PPCBIT(24) /* TX Data Snoop enable */
sys/arch/powerpc/include/booke/etsecreg.h
174
#define DMACTRL_TBDSEN __PPCBIT(25) /* TxBD Data Snoop enable */
sys/arch/powerpc/include/booke/etsecreg.h
175
#define DMACTRL_GRS __PPCBIT(27) /* graceful receive stop */
sys/arch/powerpc/include/booke/etsecreg.h
176
#define DMACTRL_GTS __PPCBIT(28) /* graceful transmit stop */
sys/arch/powerpc/include/booke/etsecreg.h
177
#define DMACTRL_TOD __PPCBIT(29) /* Transmit On Demand for TxBD ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
178
#define DMACTRL_WWR __PPCBIT(30) /* Write With Response */
sys/arch/powerpc/include/booke/etsecreg.h
179
#define DMACTRL_WOP __PPCBIT(31) /* Wait or pool for TxBD ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
187
#define TCTRL_IPCSEN __PPCBIT(17) /* IP header checksum generation enable */
sys/arch/powerpc/include/booke/etsecreg.h
188
#define TCTRL_TUCSEN __PPCBIT(18) /* TCP/UDP header checksum generation enable */
sys/arch/powerpc/include/booke/etsecreg.h
189
#define TCTRL_VLINS __PPCBIT(19) /* VLAN tag insertion */
sys/arch/powerpc/include/booke/etsecreg.h
190
#define TCTRL_THDF __PPCBIT(29) /* Transmit half duplex */
sys/arch/powerpc/include/booke/etsecreg.h
191
#define TCTRL_RFC_PAUSE __PPCBIT(27) /* receive flow control pause frame */
sys/arch/powerpc/include/booke/etsecreg.h
192
#define TCTRL_TFC_PAUSE __PPCBIT(28) /* transmit flow control pause frame */
sys/arch/powerpc/include/booke/etsecreg.h
199
#define TSTAT_THLT0 __PPCBIT(0) /* transmit halt of ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
200
#define TSTAT_THLT1 __PPCBIT(1)
sys/arch/powerpc/include/booke/etsecreg.h
201
#define TSTAT_THLT2 __PPCBIT(2)
sys/arch/powerpc/include/booke/etsecreg.h
202
#define TSTAT_THLT3 __PPCBIT(3)
sys/arch/powerpc/include/booke/etsecreg.h
203
#define TSTAT_THLT4 __PPCBIT(4)
sys/arch/powerpc/include/booke/etsecreg.h
204
#define TSTAT_THLT5 __PPCBIT(5)
sys/arch/powerpc/include/booke/etsecreg.h
205
#define TSTAT_THLT6 __PPCBIT(6)
sys/arch/powerpc/include/booke/etsecreg.h
206
#define TSTAT_THLT7 __PPCBIT(7)
sys/arch/powerpc/include/booke/etsecreg.h
209
#define TSTAT_TXF0 __PPCBIT(16) /* transmit frame event occurred on ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
210
#define TSTAT_TXF1 __PPCBIT(17)
sys/arch/powerpc/include/booke/etsecreg.h
211
#define TSTAT_TXF2 __PPCBIT(18)
sys/arch/powerpc/include/booke/etsecreg.h
212
#define TSTAT_TXF3 __PPCBIT(19)
sys/arch/powerpc/include/booke/etsecreg.h
213
#define TSTAT_TXF4 __PPCBIT(20)
sys/arch/powerpc/include/booke/etsecreg.h
214
#define TSTAT_TXF5 __PPCBIT(21)
sys/arch/powerpc/include/booke/etsecreg.h
215
#define TSTAT_TXF6 __PPCBIT(22)
sys/arch/powerpc/include/booke/etsecreg.h
216
#define TSTAT_TXF7 __PPCBIT(23)
sys/arch/powerpc/include/booke/etsecreg.h
221
#define TXIC_ICEN __PPCBIT(0) /* Interrupt coalescing enable */
sys/arch/powerpc/include/booke/etsecreg.h
222
#define TXIC_ICCS __PPCBIT(1) /* Interrupt coalescing timer clock source */
sys/arch/powerpc/include/booke/etsecreg.h
230
#define TQUEUE_EN0 __PPCBIT(16) /* transmit ring enabled */
sys/arch/powerpc/include/booke/etsecreg.h
231
#define TQUEUE_EN1 __PPCBIT(17)
sys/arch/powerpc/include/booke/etsecreg.h
232
#define TQUEUE_EN2 __PPCBIT(18)
sys/arch/powerpc/include/booke/etsecreg.h
233
#define TQUEUE_EN3 __PPCBIT(19)
sys/arch/powerpc/include/booke/etsecreg.h
234
#define TQUEUE_EN4 __PPCBIT(20)
sys/arch/powerpc/include/booke/etsecreg.h
235
#define TQUEUE_EN5 __PPCBIT(21)
sys/arch/powerpc/include/booke/etsecreg.h
236
#define TQUEUE_EN6 __PPCBIT(22)
sys/arch/powerpc/include/booke/etsecreg.h
237
#define TQUEUE_EN7 __PPCBIT(23)
sys/arch/powerpc/include/booke/etsecreg.h
274
#define RCTRL_TS __PPCBIT(7)
sys/arch/powerpc/include/booke/etsecreg.h
275
#define RCTRL_RR __PPCBIT(10)
sys/arch/powerpc/include/booke/etsecreg.h
277
#define RCTRL_VLEX __PPCBIT(18)
sys/arch/powerpc/include/booke/etsecreg.h
278
#define RCTRL_FILREN __PPCBIT(19)
sys/arch/powerpc/include/booke/etsecreg.h
279
#define RCTRL_FSQEN __PPCBIT(20)
sys/arch/powerpc/include/booke/etsecreg.h
280
#define RCTRL_GHTX __PPCBIT(21)
sys/arch/powerpc/include/booke/etsecreg.h
281
#define RCTRL_IPCSEN __PPCBIT(22)
sys/arch/powerpc/include/booke/etsecreg.h
282
#define RCTRL_TUCSEN __PPCBIT(23)
sys/arch/powerpc/include/booke/etsecreg.h
288
#define RCTRL_BC_REJ __PPCBIT(27)
sys/arch/powerpc/include/booke/etsecreg.h
289
#define RCTRL_PROM __PPCBIT(28)
sys/arch/powerpc/include/booke/etsecreg.h
290
#define RCTRL_RSF __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
291
#define RCTRL_EMEN __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
294
#define RSTAT_QHLT0 __PPCBIT(8) /* receive halt of ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
295
#define RSTAT_QHLT1 __PPCBIT(9)
sys/arch/powerpc/include/booke/etsecreg.h
296
#define RSTAT_QHLT2 __PPCBIT(10)
sys/arch/powerpc/include/booke/etsecreg.h
297
#define RSTAT_QHLT3 __PPCBIT(11)
sys/arch/powerpc/include/booke/etsecreg.h
298
#define RSTAT_QHLT4 __PPCBIT(12)
sys/arch/powerpc/include/booke/etsecreg.h
299
#define RSTAT_QHLT5 __PPCBIT(13)
sys/arch/powerpc/include/booke/etsecreg.h
300
#define RSTAT_QHLT6 __PPCBIT(14)
sys/arch/powerpc/include/booke/etsecreg.h
301
#define RSTAT_QHLT7 __PPCBIT(15)
sys/arch/powerpc/include/booke/etsecreg.h
304
#define RSTAT_RXF0 __PPCBIT(24) /* receive frame event occurred on ring 0 */
sys/arch/powerpc/include/booke/etsecreg.h
305
#define RSTAT_RXF1 __PPCBIT(25)
sys/arch/powerpc/include/booke/etsecreg.h
306
#define RSTAT_RXF2 __PPCBIT(26)
sys/arch/powerpc/include/booke/etsecreg.h
307
#define RSTAT_RXF3 __PPCBIT(27)
sys/arch/powerpc/include/booke/etsecreg.h
308
#define RSTAT_RXF4 __PPCBIT(28)
sys/arch/powerpc/include/booke/etsecreg.h
309
#define RSTAT_RXF5 __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
310
#define RSTAT_RXF6 __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
311
#define RSTAT_RXF7 __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
315
#define RXIC_ICEN __PPCBIT(0) /* Interrupt coalescing enable */
sys/arch/powerpc/include/booke/etsecreg.h
316
#define RXIC_ICCS __PPCBIT(1) /* Interrupt coalescing timer clock source */
sys/arch/powerpc/include/booke/etsecreg.h
324
#define RQUEUE_EX0 __PPCBIT(8) /* data transferred by DMA to ring extracted according to ATTR register */
sys/arch/powerpc/include/booke/etsecreg.h
325
#define RQUEUE_EX1 __PPCBIT(9)
sys/arch/powerpc/include/booke/etsecreg.h
326
#define RQUEUE_EX2 __PPCBIT(10)
sys/arch/powerpc/include/booke/etsecreg.h
327
#define RQUEUE_EX3 __PPCBIT(11)
sys/arch/powerpc/include/booke/etsecreg.h
328
#define RQUEUE_EX4 __PPCBIT(12)
sys/arch/powerpc/include/booke/etsecreg.h
329
#define RQUEUE_EX5 __PPCBIT(13)
sys/arch/powerpc/include/booke/etsecreg.h
330
#define RQUEUE_EX6 __PPCBIT(14)
sys/arch/powerpc/include/booke/etsecreg.h
331
#define RQUEUE_EX7 __PPCBIT(15)
sys/arch/powerpc/include/booke/etsecreg.h
334
#define RQUEUE_EN0 __PPCBIT(24) /* ring is queried for reception */
sys/arch/powerpc/include/booke/etsecreg.h
335
#define RQUEUE_EN1 __PPCBIT(25)
sys/arch/powerpc/include/booke/etsecreg.h
336
#define RQUEUE_EN2 __PPCBIT(26)
sys/arch/powerpc/include/booke/etsecreg.h
337
#define RQUEUE_EN3 __PPCBIT(27)
sys/arch/powerpc/include/booke/etsecreg.h
338
#define RQUEUE_EN4 __PPCBIT(28)
sys/arch/powerpc/include/booke/etsecreg.h
339
#define RQUEUE_EN5 __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
340
#define RQUEUE_EN6 __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
341
#define RQUEUE_EN7 __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
352
#define RQFCR_GPI __PPCBIT(0) /* General purpose interrupt */
sys/arch/powerpc/include/booke/etsecreg.h
359
#define RQFCR_HASH __PPCBIT(15) /* Include parser results in hash */
sys/arch/powerpc/include/booke/etsecreg.h
362
#define RQFCR_CLE __PPCBIT(22) /* Cluster entry/exit */
sys/arch/powerpc/include/booke/etsecreg.h
363
#define RQFCR_REJ __PPCBIT(23) /* Reject frame */
sys/arch/powerpc/include/booke/etsecreg.h
364
#define RQFCR_AND __PPCBIT(24) /* AND, in combination with CLE, REJ, and PID match */
sys/arch/powerpc/include/booke/etsecreg.h
388
#define RQFPR_PID1_AR __PPCBIT(14) /* ARP response */
sys/arch/powerpc/include/booke/etsecreg.h
389
#define RQFPR_PID1_ARQ __PPCBIT(15) /* ARP request */
sys/arch/powerpc/include/booke/etsecreg.h
390
#define RQFPR_PID1_EBC __PPCBIT(16) /* destination Ethernet address is to the broadcast address */
sys/arch/powerpc/include/booke/etsecreg.h
391
#define RQFPR_PID1_VLN __PPCBIT(17) /* VLAN tag */
sys/arch/powerpc/include/booke/etsecreg.h
392
#define RQFPR_PID1_CFI __PPCBIT(18) /* Canonical Format Indicator */
sys/arch/powerpc/include/booke/etsecreg.h
393
#define RQFPR_PID1_JUM __PPCBIT(19) /* Jumbo Ethernet frame */
sys/arch/powerpc/include/booke/etsecreg.h
394
#define RQFPR_PID1_IPF __PPCBIT(20) /* fragmented IPv4 or IPv6 header */
sys/arch/powerpc/include/booke/etsecreg.h
395
#define RQFPR_PID1_IP4 __PPCBIT(22) /* IPv4 header */
sys/arch/powerpc/include/booke/etsecreg.h
396
#define RQFPR_PID1_IP6 __PPCBIT(23) /* IPv6 header */
sys/arch/powerpc/include/booke/etsecreg.h
397
#define RQFPR_PID1_ICC __PPCBIT(24) /* IPv4 header checksum */
sys/arch/powerpc/include/booke/etsecreg.h
398
#define RQFPR_PID1_ICV __PPCBIT(25) /* IPv4 header checksum was verified correct */
sys/arch/powerpc/include/booke/etsecreg.h
399
#define RQFPR_PID1_TCP __PPCBIT(26) /* TCP header */
sys/arch/powerpc/include/booke/etsecreg.h
400
#define RQFPR_PID1_UDP __PPCBIT(27) /* UDP header */
sys/arch/powerpc/include/booke/etsecreg.h
401
#define RQFPR_PID1_PER __PPCBIT(30) /* parse error */
sys/arch/powerpc/include/booke/etsecreg.h
402
#define RQFPR_PID1_EER __PPCBIT(31) /* Ethernet framing error */
sys/arch/powerpc/include/booke/etsecreg.h
430
#define MACCFG1_SOFT_RESET __PPCBIT(0)
sys/arch/powerpc/include/booke/etsecreg.h
431
#define MACCFG1_RESET_RX_MAC __PPCBIT(12)
sys/arch/powerpc/include/booke/etsecreg.h
432
#define MACCFG1_RESET_TX_MAC __PPCBIT(13)
sys/arch/powerpc/include/booke/etsecreg.h
433
#define MACCFG1_RESET_RX_FUNC __PPCBIT(14)
sys/arch/powerpc/include/booke/etsecreg.h
434
#define MACCFG1_RESET_TX_FUNC __PPCBIT(15)
sys/arch/powerpc/include/booke/etsecreg.h
435
#define MACCFG1_LOOPBACK __PPCBIT(23)
sys/arch/powerpc/include/booke/etsecreg.h
436
#define MACCFG1_RX_FLOW __PPCBIT(26)
sys/arch/powerpc/include/booke/etsecreg.h
437
#define MACCFG1_TX_FLOW __PPCBIT(27)
sys/arch/powerpc/include/booke/etsecreg.h
438
#define MACCFG1_SYNC_RX_EN __PPCBIT(28)
sys/arch/powerpc/include/booke/etsecreg.h
439
#define MACCFG1_RX_EN __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
440
#define MACCFG1_SYNC_TX_EN __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
441
#define MACCFG1_TX_EN __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
448
#define MACCFG2_PRERXEN __PPCBIT(24)
sys/arch/powerpc/include/booke/etsecreg.h
449
#define MACCFG2_PRETXEN __PPCBIT(25)
sys/arch/powerpc/include/booke/etsecreg.h
450
#define MACCFG2_HG __PPCBIT(26)
sys/arch/powerpc/include/booke/etsecreg.h
451
#define MACCFG2_LENCHK __PPCBIT(27)
sys/arch/powerpc/include/booke/etsecreg.h
452
#define MACCFG2_MPEN __PPCBIT(28)
sys/arch/powerpc/include/booke/etsecreg.h
453
#define MACCFG2_PADCRC __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
454
#define MACCFG2_CRCEN __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
455
#define MACCFG2_FD __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
461
#define MIIMCFG_RESET __PPCBIT(0) /* Reset management */
sys/arch/powerpc/include/booke/etsecreg.h
462
#define MIIMCFG_NOPRE __PPCBIT(27) /* Preamble suppress */
sys/arch/powerpc/include/booke/etsecreg.h
464
#define MIIMCOM_SCAN __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
465
#define MIIMCOM_READ __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
472
#define MIIMIND_NOTVALID __PPCBIT(29)
sys/arch/powerpc/include/booke/etsecreg.h
473
#define MIIMIND_SCAN __PPCBIT(30)
sys/arch/powerpc/include/booke/etsecreg.h
474
#define MIIMIND_BUSY __PPCBIT(31)
sys/arch/powerpc/include/booke/etsecreg.h
604
#define ATTR_RDSEN __PPCBIT(24)
sys/arch/powerpc/include/booke/etsecreg.h
605
#define ATTR_RBDSEN __PPCBIT(25)
sys/arch/powerpc/include/booke/etsecreg.h
672
#define ISRG_RRn(n) __PPCBIT(n)
sys/arch/powerpc/include/booke/etsecreg.h
673
#define ISRG_TRn(n) __PPCBIT(8+(n))
