__MR
volatile u_char mfb[__MR(24)-1]; /* Sparse */
#define mf_gpip mfb[__MR(0) ] /* gen-purp I/O interrupt port */
#define mf_aer mfb[__MR(1) ] /* active edge register */
#define mf_ddr mfb[__MR(2) ] /* data direction register */
#define mf_iera mfb[__MR(3) ] /* interrupt enable register A */
#define mf_ierb mfb[__MR(4) ] /* interrupt enable register B */
#define mf_ipra mfb[__MR(5) ] /* interrupt pending register A */
#define mf_iprb mfb[__MR(6) ] /* interrupt pending register B */
#define mf_isra mfb[__MR(7) ] /* interrupt in-service register A */
#define mf_isrb mfb[__MR(8) ] /* interrupt in-service register B */
#define mf_imra mfb[__MR(9) ] /* interrupt mask register A */
#define mf_imrb mfb[__MR(10)] /* interrupt mask register B */
#define mf_vr mfb[__MR(11)] /* vector register */
#define mf_tacr mfb[__MR(12)] /* timer control register A */
#define mf_tbcr mfb[__MR(13)] /* timer control register B */
#define mf_tcdcr mfb[__MR(14)] /* timer control register C+D */
#define mf_tadr mfb[__MR(15)] /* timer data register A */
#define mf_tbdr mfb[__MR(16)] /* timer data register B */
#define mf_tcdr mfb[__MR(17)] /* timer data register C */
#define mf_tddr mfb[__MR(18)] /* timer data register D */
#define mf_scr mfb[__MR(19)] /* synchronous character register */
#define mf_ucr mfb[__MR(20)] /* USART control register */
#define mf_rsr mfb[__MR(21)] /* receiver status register */
#define mf_tsr mfb[__MR(22)] /* transmitter status register */
#define mf_udr mfb[__MR(23)] /* USART data register */