_SB_MAKE64
#define S_BCM1480_PM_DSCR0_RSVD _SB_MAKE64(0)
#define S_BCM1480_PM_DSCR0_BUFFER_LENGTH _SB_MAKE64(32)
#define S_BCM1480_PM_DSCR0_SWID _SB_MAKE64(58)
#define S_BCM1480_PM_DSCR1_BUFFER_ADDR _SB_MAKE64(0)
#define S_BCM1480_PM_DSCR1_IVC _SB_MAKE64(40)
#define S_BCM1480_PM_DSCR1_NEXT_DEST _SB_MAKE64(48)
#define S_BCM1480_PM_DSCR1_RSVD _SB_MAKE64(52)
#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000)
#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000)
#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000)
#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000)
#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000)
#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000)
#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000)
#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000)
#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000)
#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000)
#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000)
#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000)
#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000)
#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000)
#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000)
#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
#define S_DMA_OODLOST_RX _SB_MAKE64(0)
#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
#define S_DMA_DESC_TYPE _SB_MAKE64(1)
#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
#define S_DMA_RINGSZ _SB_MAKE64(16)
#define S_IO_BURST_WIDTH _SB_MAKE64(6)
#define S_MAC_SPEED_SEL _SB_MAKE64(34)
#define S_MAC_BYPASS_CFG _SB_MAKE64(40)
#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
#define S_MAC_FC_CMD _SB_MAKE64(55)
#define S_MAC_RX_CH_SEL _SB_MAKE64(57)
#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
#define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
#define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
#define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
#define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
#define S_MAC_IFG_RX _SB_MAKE64(0)
#define S_MAC_PRE_LEN _SB_MAKE64(0)
#define S_MAC_IFG_TX _SB_MAKE64(6)
#define S_MAC_IFG_THRSH _SB_MAKE64(12)
#define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
#define S_MAC_LFSR_SEED _SB_MAKE64(22)
#define S_MAC_SLOT_SIZE _SB_MAKE64(30)
#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
#define K_MAC_IFG_RX_100 _SB_MAKE64(0)
#define K_MAC_IFG_RX_1000 _SB_MAKE64(0)
#define K_MAC_IFG_TX_10 _SB_MAKE64(20)
#define K_MAC_IFG_TX_100 _SB_MAKE64(20)
#define K_MAC_IFG_TX_1000 _SB_MAKE64(8)
#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4)
#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4)
#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0)
#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9)
#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64)
#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518)
#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216)
#define S_MAC_VLAN_TAG _SB_MAKE64(0)
#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
#define S_MAC_RX_CH0 _SB_MAKE64(0)
#define S_MAC_RX_CH1 _SB_MAKE64(8)
#define S_MAC_TX_CH0 _SB_MAKE64(16)
#define S_MAC_TX_CH1 _SB_MAKE64(24)
#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */
#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */
#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
#define S_MAC_TX_WRPTR _SB_MAKE64(0)
#define S_MAC_TX_RDPTR _SB_MAKE64(8)
#define S_MAC_RX_WRPTR _SB_MAKE64(16)
#define S_MAC_RX_RDPTR _SB_MAKE64(24)
#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
#define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
#define S_TYPECFG_TYPE0 _SB_MAKE64(0)
#define S_TYPECFG_TYPE1 _SB_MAKE64(0)
#define S_TYPECFG_TYPE2 _SB_MAKE64(0)
#define S_TYPECFG_TYPE3 _SB_MAKE64(0)
#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
#define S_MAC_TX_PAUSE _SB_MAKE64(6)
#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000)
#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000)
#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000)
#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000)
#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000)
#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000)
#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000)
#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000)
#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)
#define S_SYS_L2C_SIZE _SB_MAKE64(20)
#define S_SYS_NUM_CPUS _SB_MAKE64(24)
#define S_SYS_PART _SB_MAKE64(16)
#define S_SYS_SOC_TYPE _SB_MAKE64(16)
#define S_SYS_WID _SB_MAKE64(32)
#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
#define S_SYS_BIN _SB_MAKE64(32)
#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
#define S_SYS_WAFERID_300 _SB_MAKE64(0)
#define S_SYS_XPOS _SB_MAKE64(40)
#define S_SYS_YPOS _SB_MAKE64(46)
#define S_SYS_PLL_DIV _SB_MAKE64(7)
#define S_SYS_BOOT_MODE _SB_MAKE64(17)
#define S_SYS_REVISION _SB_MAKE64(8)
#define S_DUART_SIG_FULL _SB_MAKE64(0)
#define S_DUART_INT_TIME _SB_MAKE64(4)