Symbol: _REG16
sys/arch/evbppc/nintendo/dev/gxreg.h
38
#define CP_SR _REG16(0x00)
sys/arch/evbppc/nintendo/dev/gxreg.h
41
#define CP_CR _REG16(0x02)
sys/arch/evbppc/nintendo/dev/gxreg.h
44
#define CP_CLEAR _REG16(0x04)
sys/arch/evbppc/nintendo/dev/gxreg.h
47
#define CP_FIFO_BASE_LO _REG16(0x20)
sys/arch/evbppc/nintendo/dev/gxreg.h
48
#define CP_FIFO_BASE_HI _REG16(0x22)
sys/arch/evbppc/nintendo/dev/gxreg.h
49
#define CP_FIFO_END_LO _REG16(0x24)
sys/arch/evbppc/nintendo/dev/gxreg.h
50
#define CP_FIFO_END_HI _REG16(0x26)
sys/arch/evbppc/nintendo/dev/gxreg.h
51
#define CP_FIFO_HIWAT_LO _REG16(0x28)
sys/arch/evbppc/nintendo/dev/gxreg.h
52
#define CP_FIFO_HIWAT_HI _REG16(0x2a)
sys/arch/evbppc/nintendo/dev/gxreg.h
53
#define CP_FIFO_LOWAT_LO _REG16(0x2c)
sys/arch/evbppc/nintendo/dev/gxreg.h
54
#define CP_FIFO_LOWAT_HI _REG16(0x2e)
sys/arch/evbppc/nintendo/dev/gxreg.h
55
#define CP_FIFO_RW_DIST_LO _REG16(0x30)
sys/arch/evbppc/nintendo/dev/gxreg.h
56
#define CP_FIFO_RW_DIST_HI _REG16(0x32)
sys/arch/evbppc/nintendo/dev/gxreg.h
57
#define CP_FIFO_WRITE_PTR_LO _REG16(0x34)
sys/arch/evbppc/nintendo/dev/gxreg.h
58
#define CP_FIFO_WRITE_PTR_HI _REG16(0x36)
sys/arch/evbppc/nintendo/dev/gxreg.h
59
#define CP_FIFO_READ_PTR_LO _REG16(0x38)
sys/arch/evbppc/nintendo/dev/gxreg.h
60
#define CP_FIFO_READ_PTR_HI _REG16(0x3a)
sys/arch/evbppc/nintendo/dev/gxreg.h
62
#define PE_ZCONF _REG16(0x00)
sys/arch/evbppc/nintendo/dev/gxreg.h
66
#define PE_ALPHA_CONF _REG16(0x02)
sys/arch/evbppc/nintendo/dev/gxreg.h
72
#define PE_ALPHA_DEST _REG16(0x04)
sys/arch/evbppc/nintendo/dev/gxreg.h
74
#define PE_ALPHA_MODE _REG16(0x06)
sys/arch/evbppc/nintendo/dev/gxreg.h
76
#define PE_ALPHA_READ _REG16(0x08)
sys/arch/evbppc/nintendo/dev/gxreg.h
79
#define PE_ISR _REG16(0x0a)
sys/arch/evbppc/nintendo/dev/gxreg.h
84
#define PE_TOKEN _REG16(0x0e)
sys/arch/hpcsh/dev/hd64461/hd64461video.c
1423
r = hd64461_reg_read_2(HD64461_LCD ## x ## _REG16); \