BUS_ADDR_LO32
CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
tdes->t2 = htole32(BUS_ADDR_LO32(p));
__rxd->r2 = htole32(BUS_ADDR_LO32(__p)); \
SET4(sc, CONFIG_SPACE_ADDR_OFFSET + 0x10, BUS_ADDR_LO32(base_addr));
BUS_ADDR_LO32(sc->sc_cfg_addr));
BUS_ADDR_LO32(phyaddr));
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(n), BUS_ADDR_LO32(pciaddr));
REG_WRITE0(c, GFTTY_DATA_PTR, BUS_ADDR_LO32(addr));
AHCI_WRITE(sc, AHCI_P_CLB(i), BUS_ADDR_LO32(achp->ahcic_bus_cmdh));
AHCI_WRITE(sc, AHCI_P_FB(i), BUS_ADDR_LO32(achp->ahcic_bus_rfis));
WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
#define RE_ADDR_LO(y) BUS_ADDR_LO32(y)
(x).bge_addr_lo = BUS_ADDR_LO32(y); \
BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0)));
BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0)));
BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0)));
BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0)));
bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP, BUS_ADDR_LO32(addr));
bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, BUS_ADDR_LO32(addr));
htole32(BUS_ADDR_LO32(next_desc));
htole32(BUS_ADDR_LO32(bufptr));
htole32(BUS_ADDR_LO32(next_desc));
htole32(BUS_ADDR_LO32(rxs->rxs_dmamap->dm_segs[0].ds_addr));
boot->br_hostvar_lo = htole32(BUS_ADDR_LO32(sc->sc_host_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sc->sc_txhiring_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sc->sc_txloring_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sc->sc_rxhiring_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sc->sc_rxloring_dma.dma_paddr));
boot->br_cmd_lo = htole32(BUS_ADDR_LO32(sc->sc_cmdring_dma.dma_paddr));
boot->br_resp_lo = htole32(BUS_ADDR_LO32(sc->sc_rspring_dma.dma_paddr));
boot->br_rxbuf_lo = htole32(BUS_ADDR_LO32(sc->sc_rxbufring_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr));
boot->br_zero_lo = htole32(BUS_ADDR_LO32(sc->sc_zero_dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr));
htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[i].ds_addr));
WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr));
htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr));
#define VGE_ADDR_LO(y) BUS_ADDR_LO32(y)
wa->wa_low = htole32(BUS_ADDR_LO32(v));
bus_space_write_4(iot, ioh, offset, BUS_ADDR_LO32(value));
sqh->physaddr = BUS_ADDR_LO32(baddr);
sqtd->physaddr = BUS_ADDR_LO32(baddr);
sqtd->qtd->qtd_buffer[i] = htole32(BUS_ADDR_LO32(a));
itd->physaddr = BUS_ADDR_LO32(baddr);
sitd->physaddr = BUS_ADDR_LO32(baddr);
setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
setup->qtd->qtd_buffer[0] = htole32(BUS_ADDR_LO32(ba));
sitd->sitd->sitd_buffer[0] = htole32(BUS_ADDR_LO32(sba));
htole32(EHCI_SITD_SET_BPTR(BUS_ADDR_LO32(eba)));
const uint32_t lo32 = BUS_ADDR_LO32(flba);
virtio_mmio_reg_write(sc, reg, BUS_ADDR_LO32(addr));