BUS_ADDR_HI32
CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
tdes->t1 = htole32(BUS_ADDR_HI32(p));
__rxd->r1 = htole32(BUS_ADDR_HI32(__p)); \
SET4(sc, CONFIG_SPACE_ADDR_OFFSET + 0x14, BUS_ADDR_HI32(base_addr));
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(0), BUS_ADDR_HI32(sc->sc_cfg_addr));
WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(n), BUS_ADDR_HI32(phyaddr));
WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(n), BUS_ADDR_HI32(pciaddr));
REG_WRITE0(c, GFTTY_DATA_PTR_HIGH, BUS_ADDR_HI32(addr));
AHCI_WRITE(sc, AHCI_P_CLBU(i), BUS_ADDR_HI32(achp->ahcic_bus_cmdh));
AHCI_WRITE(sc, AHCI_P_FBU(i), BUS_ADDR_HI32(achp->ahcic_bus_rfis));
WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr));
WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr));
#define RE_ADDR_HI(y) BUS_ADDR_HI32(y)
(x).bge_addr_hi = BUS_ADDR_HI32(y); \
BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0)));
BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0)));
BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0)));
BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0)));
BUS_ADDR_HI32(addr));
BUS_ADDR_HI32(addr));
htole32(BUS_ADDR_HI32(next_desc));
htole32(BUS_ADDR_HI32(bufptr));
htole32(BUS_ADDR_HI32(next_desc));
htole32(BUS_ADDR_HI32(rxs->rxs_dmamap->dm_segs[0].ds_addr));
boot->br_hostvar_hi = htole32(BUS_ADDR_HI32(sc->sc_host_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sc->sc_txhiring_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sc->sc_txloring_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sc->sc_rxhiring_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sc->sc_rxloring_dma.dma_paddr));
boot->br_cmd_hi = htole32(BUS_ADDR_HI32(sc->sc_cmdring_dma.dma_paddr));
boot->br_resp_hi = htole32(BUS_ADDR_HI32(sc->sc_rspring_dma.dma_paddr));
boot->br_rxbuf_hi = htole32(BUS_ADDR_HI32(sc->sc_rxbufring_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr));
boot->br_zero_hi = htole32(BUS_ADDR_HI32(sc->sc_zero_dma.dma_paddr));
WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr));
htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[i].ds_addr));
WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr));
htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr));
#define VGE_ADDR_HI(y) BUS_ADDR_HI32(y)
wa->wa_high = htole32(BUS_ADDR_HI32(v));
bus_space_write_4(iot, ioh, offset + 4, BUS_ADDR_HI32(value));
KASSERT(BUS_ADDR_HI32(baddr) == 0);
KASSERT(BUS_ADDR_HI32(baddr) == 0);
sqtd->qtd->qtd_buffer_hi[i] = htole32(BUS_ADDR_HI32(a));
KASSERT(BUS_ADDR_HI32(baddr) == 0);
KASSERT(BUS_ADDR_HI32(baddr) == 0);
setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
setup->qtd->qtd_buffer_hi[0] = htole32(BUS_ADDR_HI32(ba));
sitd->sitd->sitd_buffer_hi[0] = htole32(BUS_ADDR_HI32(sba));
sitd->sitd->sitd_buffer_hi[1] = htole32(BUS_ADDR_HI32(eba));
const uint32_t hi32 = BUS_ADDR_HI32(flba);
virtio_mmio_reg_write(sc, reg + 4, BUS_ADDR_HI32(addr));