sys/arch/arm/nvidia/tegra210_xusbpad.c

246

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

319

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

321

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

325

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

334

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

338

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

347

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

356

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,