sys/arch/arm/nvidia/tegra210_xusbpad.c

242

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

258

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

261

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

264

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

267

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

269

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

305

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

309

val = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG);

sys/arch/arm/nvidia/tegra210_xusbpad.c

352

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,