sys/arch/luna68k/dev/lunaws.c

234

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna68k/dev/siotty.c

194

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna68k/dev/siotty.c

431

sc->sc_wr[WR3] &= ~WR3_RX8BIT;

sys/arch/luna68k/dev/siotty.c

435

sc->sc_wr[WR3] |= WR3_RX7BIT;

sys/arch/luna68k/dev/siotty.c

439

sc->sc_wr[WR3] |= WR3_RX8BIT;

sys/arch/luna68k/dev/siotty.c

453

setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);

sys/arch/luna68k/dev/siotty.c

723

setsioreg(sio, WR3, ch0_regs[WR3]);

sys/arch/luna68k/stand/boot/sio.c

228

sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL);

sys/arch/luna68k/stand/boot/sio.c

244

sioreg(REG(1, WR3), WR3_RX8BIT | WR3_RXENBL);