WR2
WR2(sc, MUSB2_REG_INTTX, inttx);
WR2(sc, MUSB2_REG_INTRX, intrx);
WR2(avenc_tag, avenc_addr, AVENC_VOLUME, val);
WR2(tag, addr, 0x05, 0);
WR2(tag, addr, 0x08, 0);
WR2(tag, addr, 0x08, 0);
WR2(sc, sc->sc_dma_start_addr_h, phys_addr >> 16);
WR2(sc, sc->sc_dma_start_addr_l, phys_addr & 0xffff);
WR2(sc, sc->sc_dma_control_length,
WR2(sc, sc->sc_dma_control_length, 0);
WR2(sc, VI_DCR, VI_DCR_RST);
WR2(sc, VI_DCR, dcr);
WR2(sc, VI_VTR, 0x0f06);
WR2(sc, VI_DPV, 0x0000);
WR2(sc, VI_DPH, 0x0000);
WR2(sc, VI_VTR, 0x1e0c);
WR2(sc, VI_DPV, 0x0000);
WR2(sc, VI_DPH, 0x0000);
WR2(sc, VI_VTR, 0x11f5);
WR2(sc, VI_DPV, 0x013c);
WR2(sc, VI_DPH, 0x0144);
WR2(sc, VI_UNKNOWN_76H, 0x00ff);
WR2(sc, VI_PICCONF,
WR2(sc, VI_HSR, __SHIFTIN(256, VI_HSR_STP));
WR2(sc, VI_HSR, __SHIFTIN(244, VI_HSR_STP) | VI_HSR_HS_EN);
WR2(sc, VI_VICLK,
WR2(sc, VI_HSCALINGW, sc->sc_curmode->width);
WR2(sc, VI_DCR, RD2(sc, VI_DCR) | VI_DCR_ENB);
#define WR2A WR2 /* on channel A */
#define WR2B WR2 /* on channel B */
WR2(sc, PSC_TFALARM, MPCAC97_TFALARM);
WR2(sc, PSC_IMR, 0); /* no PSC interrupts; BestComm drives playback */