sys/arch/arm/ti/ti_omapmusb.c

107

WR1(sc, MUSB2_REG_INTUSB, intusb);

sys/arch/evbppc/nintendo/dev/avenc.c

206

WR1(tag, addr, 0x6a, 1);

sys/arch/evbppc/nintendo/dev/avenc.c

207

WR1(tag, addr, 0x65, 3);

sys/arch/evbppc/nintendo/dev/avenc.c

208

WR1(tag, addr, 0x01, video_fmt);

sys/arch/evbppc/nintendo/dev/avenc.c

209

WR1(tag, addr, 0x00, 0);

sys/arch/evbppc/nintendo/dev/avenc.c

210

WR1(tag, addr, 0x02, 7);

sys/arch/evbppc/nintendo/dev/avenc.c

215

WR1(tag, addr, 0x0a, 0);

sys/arch/evbppc/nintendo/dev/avenc.c

216

WR1(tag, addr, 0x03, 1);

sys/arch/evbppc/nintendo/dev/avenc.c

218

WR1(tag, addr, 0x04, 1);

sys/arch/evbppc/nintendo/dev/avenc.c

221

WR1(tag, addr, 0x03, 1);

sys/arch/evbppc/nintendo/dev/avenc.c

222

WR1(tag, addr, 0x6e, 0);

sys/arch/luna68k/dev/lunaws.c

250

setsioreg(sc->sc_ctl, WR1, sc->sc_wr[WR1]);

sys/arch/luna68k/dev/siotty.c

198

setsioreg(sc->sc_ctl, WR1, sc->sc_wr[WR1]); /* now interrupt driven */

sys/arch/luna68k/stand/boot/sio.c

234

sioreg(REG(0, WR1), WR1_RXALLS);

sys/arch/luna68k/stand/boot/sio.c

250

sioreg(REG(1, WR1), WR1_RXALLS);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

318

WR1(sc, PSC_CR, CMD_RESET_RX);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

319

WR1(sc, PSC_CR, CMD_RESET_TX);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

320

WR1(sc, PSC_CR, CMD_RESET_ERR);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

321

WR1(sc, PSC_CR, CMD_RESET_MR);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

327

WR1(sc, PSC_TFCNTL, MPCAC97_TFGRAN);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

429

WR1(sc, PSC_CR, CMD_TX_DISABLE | CMD_RX_DISABLE);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

430

WR1(sc, PSC_OP1, AC97_OP_RES); /* RES -> low */

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

432

WR1(sc, PSC_OP0, AC97_OP_RES); /* RES -> high */

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

434

WR1(sc, PSC_CR, CMD_TX_ENABLE | CMD_RX_ENABLE);