sys/arch/evbppc/virtex/design_gsrd1.c

107

WCASE(DCR_XLCOM_BASE, XLCOM_TX_FIFO);

sys/arch/evbppc/virtex/design_gsrd1.c

108

WCASE(DCR_XLCOM_BASE, XLCOM_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

109

WCASE(DCR_XLCOM_BASE, XLCOM_CNTL);

sys/arch/evbppc/virtex/design_gsrd1.c

138

WCASE(DCR_LLFB_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd1.c

171

WCASE(DCR_CDMAC_BASE, CDMAC_INTR);

sys/arch/evbppc/virtex/design_gsrd1.c

172

WCASE(DCR_CDMAC_BASE, CDMAC_TX0_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

173

WCASE(DCR_CDMAC_BASE, CDMAC_RX0_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

174

WCASE(DCR_CDMAC_BASE, CDMAC_TX1_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

175

WCASE(DCR_CDMAC_BASE, CDMAC_RX1_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

176

DOCHAN(WCASE, CDMAC_TX0_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

177

DOCHAN(WCASE, CDMAC_RX0_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

178

DOCHAN(WCASE, CDMAC_TX1_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

179

DOCHAN(WCASE, CDMAC_RX1_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

216

WCASE(DCR_TEMAC_BASE, TEMAC_RESET);

sys/arch/evbppc/virtex/design_gsrd2.c

106

WCASE(DCR_TFT0_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd2.c

107

WCASE(DCR_TFT0_BASE, TFT_ADDR);

sys/arch/evbppc/virtex/design_gsrd2.c

136

WCASE(DCR_TFT1_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd2.c

137

WCASE(DCR_TFT0_BASE, TFT_ADDR);

sys/arch/evbppc/virtex/design_gsrd2.c

171

WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

172

WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

173

WCASE(DCR_CDMAC_BASE, CDMAC_INTR);

sys/arch/evbppc/virtex/design_gsrd2.c

174

DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));

sys/arch/evbppc/virtex/design_gsrd2.c

175

DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));

sys/arch/evbppc/virtex/design_gsrd2.c

208

WCASE(DCR_TEMAC_BASE, TEMAC_RESET);