sys/arch/hpcmips/stand/lcboot/com.c

110

while (!ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_TXRDY)

sys/arch/hpcmips/stand/lcboot/com.c

114

REGWRITE_1(VR4181_SIU_ADDR, com_data, c);

sys/arch/hpcmips/stand/lcboot/com.c

118

while (!ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_TXRDY)

sys/arch/hpcmips/stand/lcboot/com.c

140

REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_DLAB);

sys/arch/hpcmips/stand/lcboot/com.c

142

REGWRITE_1(VR4181_SIU_ADDR, com_dlbl, rate);

sys/arch/hpcmips/stand/lcboot/com.c

143

REGWRITE_1(VR4181_SIU_ADDR, com_dlbh, rate >> 8);

sys/arch/hpcmips/stand/lcboot/com.c

149

REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_8BITS);

sys/arch/hpcmips/stand/lcboot/com.c

152

REGWRITE_1(VR4181_SIU_ADDR, com_ier, 0);

sys/arch/hpcmips/stand/lcboot/com.c

155

REGWRITE_1(VR4181_SIU_ADDR, com_fifo,

sys/arch/hpcmips/stand/lcboot/com.c

159

REGWRITE_1(VR4181_SIU_ADDR, com_mcr, MCR_DTR | MCR_RTS);

sys/arch/hpcmips/stand/lcboot/com.c

84

return ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_RXRDY);

sys/arch/hpcmips/stand/lcboot/com.c

97

c = REGREAD_1(VR4181_SIU_ADDR, com_data);

sys/arch/hpcmips/stand/lcboot/com.c

98

stat = REGREAD_1(VR4181_SIU_ADDR, com_iir);

sys/arch/hpcmips/stand/lcboot/extern.h

100

#define ISKEY ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_RXRDY)

sys/arch/hpcmips/vr/vripreg.h

165

#define VRIP_SIU_ADDR VR4181_SIU_ADDR