sys/arch/hpcmips/stand/lcboot/main.c

242

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);

sys/arch/hpcmips/stand/lcboot/main.c

243

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

256

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W, GP8_GPO);

sys/arch/hpcmips/stand/lcboot/main.c

268

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

281

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

298

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);

sys/arch/hpcmips/stand/lcboot/main.c

299

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

314

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

328

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

341

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

356

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTTYP_L_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

358

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTMASK_REG_W,

sys/arch/hpcmips/stand/lcboot/main.c

360

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTEN_REG_W, GIEN4);

sys/arch/hpcmips/stand/lcboot/main.c

374

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STRA_REG_W, 0x0000);

sys/arch/hpcmips/stand/lcboot/main.c

375

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STPA_REG_W, 0x0fff);

sys/arch/hpcmips/stand/lcboot/main.c

376

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0HIA_REG_W, 0x1401);

sys/arch/hpcmips/stand/lcboot/main.c

377

REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCSMODE_REG_W,

sys/arch/hpcmips/vr/vripreg.h

173

#define VRIP_GIU81_ADDR VR4181_GIU81_ADDR