sys/arch/arm/ep93xx/ep93xx_intr.c

101

if (irq < VIC_NIRQ) {

sys/arch/arm/ep93xx/ep93xx_intr.c

105

vic2_intr_enabled &= ~(1U << (irq - VIC_NIRQ));

sys/arch/arm/ep93xx/ep93xx_intr.c

106

VIC2REG(EP93XX_VIC_IntEnClear) = (1U << (irq - VIC_NIRQ));

sys/arch/arm/ep93xx/ep93xx_intr.c

135

for (irq = 0; irq < VIC_NIRQ; irq++) {

sys/arch/arm/ep93xx/ep93xx_intr.c

140

for (irq = 0; irq < VIC_NIRQ; irq++) {

sys/arch/arm/ep93xx/ep93xx_intr.c

141

if (intrq[irq + VIC_NIRQ].iq_levels & (1U << ipl))

sys/arch/arm/ep93xx/ep93xx_intr.c

178

if (irq < VIC_NIRQ) {

sys/arch/arm/ep93xx/ep93xx_intr.c

183

vic2_irqs = (1U << (irq - VIC_NIRQ));

sys/arch/arm/ep93xx/ep93xx_intr.c

284

NULL, (i < VIC_NIRQ ? "vic1" : "vic2"),

sys/arch/arm/ep93xx/ep93xx_intr.c

370

iq = &intrq[irq + VIC_NIRQ];

sys/arch/arm/ep93xx/ep93xx_intr.c

89

if (irq < VIC_NIRQ) {

sys/arch/arm/ep93xx/ep93xx_intr.c

93

vic2_intr_enabled |= (1U << (irq - VIC_NIRQ));

sys/arch/arm/ep93xx/ep93xx_intr.c

94

VIC2REG(EP93XX_VIC_IntEnable) = (1U << (irq - VIC_NIRQ));