VIASR
VIASR);
uni_load_reg(sc, val, regnum, reg, VIASR);
uni_load_reg(sc, val, regnum, reg, VIASR);
uni_load_reg(sc, val, regnum, reg, VIASR);
uni_load_reg(sc, val, regnum, reg, VIASR);
uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe);
uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe);
uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe);
uni_wr(sc, VIASR, SR44, clk / 0x10000);
uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);
uni_wr(sc, VIASR, SR46, clk % 0x100);
uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1);
uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1);
uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0);
uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6);
uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6);
val = uni_rd(sc, VIASR, SR30);
val = uni_rd(sc, VIASR, SR39);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1,
uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
uni_wr_mask(sc, VIASR, cridx, data, regmask);
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIASR,SR10,0xFF,0x01},
{VIASR,SR15,0x02,0x02},
{VIASR,SR16,0xBF,0x08},
{VIASR,SR17,0xFF,0x1F},
{VIASR,SR18,0xFF,0x4E},
{VIASR,SR1A,0xFB,0x82},
{VIASR,SR1B,0xFF,0xF0},
{VIASR,SR1F,0xFF,0x00},
{VIASR,SR1E,0xFF,0xF1},
{VIASR,SR22,0xFF,0x1F},
{VIASR,SR2A,0x0F,0x0F},
{VIASR,SR2E,0xFF,0xFF},
{VIASR,SR3F,0xFF,0xFF},
{VIASR,SR40,0xFF,0x00},
{VIASR,CR30,0xFF,0x04},
{VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
{VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
{VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
{VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
{VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
{VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
{VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
{VIASR, SR1E, 0x0F, 0x01}, /* Power Management Control */
{VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
{VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
{VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
{VIASR, SR2A, 0xF0, 0x00}, /* Power Management Control 5 */
{VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
{VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIASR,SR1E,0xF0,0xF0},
{VIASR,SR2A,0x0F,0x0F},
{VIASR,SR15,0x02,0x02},
{VIASR,SR16,0xBF,0x08},
{VIASR,SR17,0xFF,0x1F},
{VIASR,SR18,0xFF,0x4E},
{VIASR,SR1A,0xFB,0x08},
{VIASR,0x16,0xBF,0x0C},
{VIASR,0x18,0xFF,0x4C}
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},