sys/arch/mips/cavium/dev/octeon_dwctwo.c

199

clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

218

octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

222

octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_HCLK_RST);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

234

clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

236

octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

250

octeon_dwc2_reg_deassert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_POR);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

278

octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_PRST);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

294

octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_HRST);

sys/arch/mips/cavium/dev/octeon_dwctwo.c

299

octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_ENABLE);