sys/arch/arm/marvell/armadaxpreg.h

404

#define ARMADAXP_PEX10_BASE (UNITID2PHYS(PEX1))

sys/arch/arm/marvell/armadaxpreg.h

408

#define ARMADAXP_PEX2_BASE (UNITID2PHYS(PEX2) + 0x2000)

sys/arch/arm/marvell/armadaxpreg.h

409

#define ARMADAXP_PEX3_BASE (UNITID2PHYS(PEX3) + 0x2000)

sys/arch/arm/marvell/armadaxpreg.h

414

#define ARMADAXP_USB_BASE (UNITID2PHYS(USB)) /* 0x50000 */

sys/arch/arm/marvell/armadaxpreg.h

422

#define ARMADAXP_XORE0_BASE (UNITID2PHYS(XORE0)) /* 0x60000 */

sys/arch/arm/marvell/armadaxpreg.h

423

#define ARMADAXP_XORE1_BASE (UNITID2PHYS(XORE1)) /* 0xf0000 */

sys/arch/arm/marvell/armadaxpreg.h

428

#define ARMADAXP_GBE0_BASE (UNITID2PHYS(GBE0)) /* 0x70000 */

sys/arch/arm/marvell/armadaxpreg.h

430

#define ARMADAXP_GBE2_BASE (UNITID2PHYS(GBE2)) /* 0x30000 */

sys/arch/arm/marvell/armadaxpreg.h

436

#define ARMADAXP_PTP_BASE (UNITID2PHYS(GBE0)) /* 0x7c000 */

sys/arch/arm/marvell/armadaxpreg.h

441

#define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */

sys/arch/arm/marvell/armadaxpreg.h

442

#define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */

sys/arch/arm/marvell/armadaxpreg.h

444

#define ARMADAXP_XPSEC0_BASE (UNITID2PHYS(CRYPT) + 0x0000) /* 0x90000 */

sys/arch/arm/marvell/armadaxpreg.h

445

#define ARMADAXP_XPSEC1_BASE (UNITID2PHYS(CRYPT) + 0x2000) /* 0x92000 */

sys/arch/arm/marvell/armadaxpreg.h

450

#define ARMADAXP_SATAHC_BASE (UNITID2PHYS(SATA)) /* 0xa0000 */

sys/arch/arm/marvell/armadaxpreg.h

455

#define ARMADAXP_BMC_BASE (UNITID2PHYS(BM)) /* 0xc0000 */

sys/arch/arm/marvell/armadaxpreg.h

465

#define ARMADAXP_PNC_BASE (UNITID2PHYS(PNC)) /* 0xc8000 */

sys/arch/arm/marvell/armadaxpreg.h

470

#define ARMADAXP_SDIO_BASE (UNITID2PHYS(SDIO) + 0x4000) /* 0xd4000 */

sys/arch/arm/marvell/armadaxpreg.h

475

#define ARMADAXP_LCD_BASE (UNITID2PHYS(LCD)) /* 0xe0000 */

sys/arch/arm/marvell/mvsocreg.h

197

#define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */

sys/arch/arm/marvell/mvsocreg.h

50

#define MVSOC_DDR_BASE (UNITID2PHYS(DDR)) /* 0x00000 */

sys/arch/arm/marvell/mvsocreg.h

64

#define MVSOC_DEVBUS_BASE (UNITID2PHYS(DEVBUS)) /* 0x10000 */

sys/arch/arm/marvell/mvsocreg.h

86

#define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */