common/lib/libc/gen/radixtree.c
1171
offset + i * (UINT64_C(1) <<
common/lib/libc/gen/radixtree.c
1316
assert(radix_tree_insert_node(t, UINT64_C(10000000000), (void *)0xdea0)
common/lib/libc/gen/radixtree.c
1321
assert(radix_tree_lookup_node(t, UINT64_C(10000000000)) ==
common/lib/libc/gen/radixtree.c
1326
assert(!radix_tree_get_tag(t, UINT64_C(10000000000), 1));
common/lib/libc/gen/radixtree.c
1328
radix_tree_set_tag(t, UINT64_C(10000000000), 2);
common/lib/libc/gen/radixtree.c
1332
assert(radix_tree_get_tag(t, UINT64_C(10000000000), 2));
common/lib/libc/gen/radixtree.c
1334
radix_tree_clear_tag(t, UINT64_C(10000000000), 2);
common/lib/libc/gen/radixtree.c
1338
assert(!radix_tree_get_tag(t, UINT64_C(10000000000), 2));
common/lib/libc/gen/radixtree.c
1362
assert(radix_tree_gang_lookup_node(t, UINT64_C(10000000001), results, 3,
common/lib/libc/gen/radixtree.c
1364
assert(radix_tree_gang_lookup_node(t, UINT64_C(10000000001), results, 3,
common/lib/libc/gen/radixtree.c
1366
assert(radix_tree_gang_lookup_node(t, UINT64_C(1000000000000), results,
common/lib/libc/gen/radixtree.c
1368
assert(radix_tree_gang_lookup_node(t, UINT64_C(1000000000000), results,
common/lib/libc/gen/radixtree.c
1380
assert(radix_tree_insert_node(t, UINT64_C(10000000001), (void *)0xfff0)
common/lib/libc/gen/radixtree.c
1383
assert(radix_tree_gang_lookup_node(t, UINT64_C(10000000000), results, 3,
common/lib/libc/gen/radixtree.c
1388
assert(radix_tree_gang_lookup_node(t, UINT64_C(10000000000), results, 3,
common/lib/libc/gen/radixtree.c
1393
assert(radix_tree_gang_lookup_node_reverse(t, UINT64_C(10000000001),
common/lib/libc/gen/radixtree.c
1399
assert(radix_tree_gang_lookup_node_reverse(t, UINT64_C(10000000001),
common/lib/libc/gen/radixtree.c
1403
assert(radix_tree_remove_node(t, UINT64_C(10000000000)) ==
common/lib/libc/gen/radixtree.c
1405
assert(radix_tree_remove_node(t, UINT64_C(10000000001)) ==
common/lib/libc/gen/radixtree.c
509
const uint64_t mask = (UINT64_C(1) << RADIX_TREE_BITS_PER_HEIGHT) - 1;
common/lib/libc/gen/rpst.c
100
return (UINT64_C(1) << (height + 1)) - 1;
common/lib/libc/gen/rpst.c
117
mask = UINT64_C(1) << (t->t_height - level);
sbin/gpt/gpt_uuid.c
351
u->time_low = x & UINT64_C(0xffffffff);
sys/arch/alpha/tc/tc_bus_mem.c
487
((UINT64_C(msk) << (32 + (b))) | ((uint64_t)(v) << ((b) << 3)))
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
100
#define MIO_BOOT_ERR_XXX_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
101
#define MIO_BOOT_ERR_WAIT_ERR UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
102
#define MIO_BOOT_ERR_ADR_ERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
104
#define MIO_BOOT_INT_XXX_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
105
#define MIO_BOOT_INT_WAIT_INT UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
106
#define MIO_BOOT_INT_ADR_INT UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
108
#define MIO_BOOT_THR_XXX_63_14 UINT64_C(0xffffffffffffc000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
109
#define MIO_BOOT_THR_FIF_CNT UINT64_C(0x0000000000003f00)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
110
#define MIO_BOOT_THR_XXX_7_6 UINT64_C(0x00000000000000c0)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
111
#define MIO_BOOT_THR_FIF_THR UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
113
#define MIO_BOOT_BIST_STAT_XXX_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
114
#define MIO_BOOT_BIST_STAT_NCBO_1 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
115
#define MIO_BOOT_BIST_STAT_NCBO_0 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
116
#define MIO_BOOT_BIST_STAT_LOC UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
117
#define MIO_BOOT_BIST_STAT_NCBI UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
65
#define MIO_BOOT_REG_CFGN_XXX_63_37 UINT64_C(0xffffffe000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
66
#define MIO_BOOT_REG_CFGN_SAM UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
67
#define MIO_BOOT_REG_CFGN_WE_EXT UINT64_C(0x0000000c00000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
68
#define MIO_BOOT_REG_CFGN_OE_EXT UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
69
#define MIO_BOOT_REG_CFGN_EN UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
70
#define MIO_BOOT_REG_CFGN_OR UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
71
#define MIO_BOOT_REG_CFGN_ALE UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
72
#define MIO_BOOT_REG_CFGN_WIDTH UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
73
#define MIO_BOOT_REG_CFGN_SIZE UINT64_C(0x000000000fff0000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
74
#define MIO_BOOT_REG_CFGN_BASE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
76
#define MIO_BOOT_REG_TIMN_PAGEM UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
77
#define MIO_BOOT_REG_TIMN_WAITM UINT64_C(0x4000000000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
78
#define MIO_BOOT_REG_TIMN_PAGES UINT64_C(0x3000000000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
79
#define MIO_BOOT_REG_TIMN_ALE UINT64_C(0x0fc0000000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
80
#define MIO_BOOT_REG_TIMN_PAGE UINT64_C(0x003f000000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
81
#define MIO_BOOT_REG_TIMN_WAIT UINT64_C(0x0000fc0000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
82
#define MIO_BOOT_REG_TIMN_PAUSE UINT64_C(0x000003f000000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
83
#define MIO_BOOT_REG_TIMN_WR_HLD UINT64_C(0x0000000fc0000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
84
#define MIO_BOOT_REG_TIMN_RD_HLD UINT64_C(0x000000003f000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
85
#define MIO_BOOT_REG_TIMN_WE UINT64_C(0x0000000000fc0000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
86
#define MIO_BOOT_REG_TIMN_OE UINT64_C(0x000000000003f000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
87
#define MIO_BOOT_REG_TIMN_CE UINT64_C(0x0000000000000fc0)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
88
#define MIO_BOOT_REG_TIMN_ADR UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
90
#define MIO_BOOT_LOC_CFGN_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
91
#define MIO_BOOT_LOC_CFGN_EN UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
92
#define MIO_BOOT_LOC_CFGN_XXX_30_28 UINT64_C(0x0000000070000000)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
93
#define MIO_BOOT_LOC_CFGN_BASE UINT64_C(0x000000000ffffff8)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
94
#define MIO_BOOT_LOC_CFGN_XXX_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
96
#define MIO_BOOT_LOC_ADR_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
97
#define MIO_BOOT_LOC_ADR_ADR UINT64_C(0x00000000000000f8)
sys/arch/mips/cavium/dev/octeon_bootbusreg.h
98
#define MIO_BOOT_LOC_ADR_XXX_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_ciureg.h
224
#define CIU_TIMX_XXX_63_37 UINT64_C(0xffffffe000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
225
#define CIU_TIMX_ONE_SHOT UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
226
#define CIU_TIMX_LEN UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
228
#define CIU_WDOGX_XXX_63_46 UINT64_C(0xffffc00000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
229
#define CIU_WDOGX_GSTOPEN UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
230
#define CIU_WDOGX_DSTOP UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
231
#define CIU_WDOGX_CNT UINT64_C(0x00000ffffff00000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
232
#define CIU_WDOGX_LEN UINT64_C(0x00000000000ffff0)
sys/arch/mips/cavium/dev/octeon_ciureg.h
233
#define CIU_WDOGX_STATE UINT64_C(0x000000000000000c)
sys/arch/mips/cavium/dev/octeon_ciureg.h
234
#define CIU_WDOGX_MODE UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_ciureg.h
240
#define CIU_PP_POKEX_XXX_63_0 UINT64_C(0xffffffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
242
#define CIU_MBOX_SETX_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
243
#define CIU_MBOX_SETX_SET UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
245
#define CIU_MBOX_CLRX_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
246
#define CIU_MBOX_CLRX_CLR UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
248
#define CIU_PP_RST_RST UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
249
#define CIU_PP_RST_RST0 UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ciureg.h
251
#define CIU_PP_DBG_PPDBG UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
253
#define CIU_GSTOP_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_ciureg.h
254
#define CIU_GSTOP_GSTOP UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ciureg.h
256
#define CIU_NMI_NMI UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
258
#define CIU_DINT_DINT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
260
#define CIU_FUSE_FUSE UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
262
#define CIU_BIST_BIST UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_ciureg.h
264
#define CIU_SOFT_BIST_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_ciureg.h
265
#define CIU_SOFT_BIST_SOFT_BIST UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ciureg.h
267
#define CIU_SOFT_RST_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_ciureg.h
268
#define CIU_SOFT_RST_SOFT_RST UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ciureg.h
270
#define CIU_SOFT_PRST_XXX_63_4 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_ciureg.h
271
#define CIU_SOFT_PRST_HOST64 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_ciureg.h
272
#define CIU_SOFT_PRST_NPI UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_ciureg.h
273
#define CIU_SOFT_PRST_SOFT_PRST UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ciureg.h
275
#define CIU_PCI_INTA_XXX_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_ciureg.h
276
#define CIU_PCI_INTA_INT UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_ciureg.h
38
#define CIU_INT0_SUM0 UINT64_C(0x0001070000000000)
sys/arch/mips/cavium/dev/octeon_ciureg.h
39
#define CIU_INT1_SUM0 UINT64_C(0x0001070000000008)
sys/arch/mips/cavium/dev/octeon_ciureg.h
40
#define CIU_INT2_SUM0 UINT64_C(0x0001070000000010)
sys/arch/mips/cavium/dev/octeon_ciureg.h
41
#define CIU_INT3_SUM0 UINT64_C(0x0001070000000018)
sys/arch/mips/cavium/dev/octeon_ciureg.h
44
#define CIU_INT32_SUM0 UINT64_C(0x0001070000000100)
sys/arch/mips/cavium/dev/octeon_ciureg.h
45
#define CIU_INT_SUM1 UINT64_C(0x0001070000000108)
sys/arch/mips/cavium/dev/octeon_ciureg.h
46
#define CIU_INT0_EN0 UINT64_C(0x0001070000000200)
sys/arch/mips/cavium/dev/octeon_ciureg.h
47
#define CIU_INT1_EN0 UINT64_C(0x0001070000000210)
sys/arch/mips/cavium/dev/octeon_ciureg.h
48
#define CIU_INT2_EN0 UINT64_C(0x0001070000000220)
sys/arch/mips/cavium/dev/octeon_ciureg.h
49
#define CIU_INT3_EN0 UINT64_C(0x0001070000000230)
sys/arch/mips/cavium/dev/octeon_ciureg.h
52
#define CIU_INT32_EN0 UINT64_C(0x0001070000000400)
sys/arch/mips/cavium/dev/octeon_ciureg.h
53
#define CIU_INT0_EN1 UINT64_C(0x0001070000000208)
sys/arch/mips/cavium/dev/octeon_ciureg.h
54
#define CIU_INT1_EN1 UINT64_C(0x0001070000000218)
sys/arch/mips/cavium/dev/octeon_ciureg.h
55
#define CIU_INT2_EN1 UINT64_C(0x0001070000000228)
sys/arch/mips/cavium/dev/octeon_ciureg.h
56
#define CIU_INT3_EN1 UINT64_C(0x0001070000000238)
sys/arch/mips/cavium/dev/octeon_ciureg.h
59
#define CIU_INT32_EN1 UINT64_C(0x0001070000000408)
sys/arch/mips/cavium/dev/octeon_ciureg.h
60
#define CIU_TIM0 UINT64_C(0x0001070000000480)
sys/arch/mips/cavium/dev/octeon_ciureg.h
61
#define CIU_TIM1 UINT64_C(0x0001070000000488)
sys/arch/mips/cavium/dev/octeon_ciureg.h
62
#define CIU_TIM2 UINT64_C(0x0001070000000490)
sys/arch/mips/cavium/dev/octeon_ciureg.h
63
#define CIU_TIM3 UINT64_C(0x0001070000000498)
sys/arch/mips/cavium/dev/octeon_ciureg.h
64
#define CIU_WDOG0 UINT64_C(0x0001070000000500)
sys/arch/mips/cavium/dev/octeon_ciureg.h
66
#define CIU_PP_POKE0 UINT64_C(0x0001070000000580)
sys/arch/mips/cavium/dev/octeon_ciureg.h
67
#define CIU_PP_POKE1 UINT64_C(0x0001070000000588)
sys/arch/mips/cavium/dev/octeon_ciureg.h
69
#define CIU_MBOX_SET0 UINT64_C(0x0001070000000600)
sys/arch/mips/cavium/dev/octeon_ciureg.h
70
#define CIU_MBOX_SET1 UINT64_C(0x0001070000000608)
sys/arch/mips/cavium/dev/octeon_ciureg.h
72
#define CIU_MBOX_CLR0 UINT64_C(0x0001070000000680)
sys/arch/mips/cavium/dev/octeon_ciureg.h
73
#define CIU_MBOX_CLR1 UINT64_C(0x0001070000000688)
sys/arch/mips/cavium/dev/octeon_ciureg.h
75
#define CIU_PP_RST UINT64_C(0x0001070000000700)
sys/arch/mips/cavium/dev/octeon_ciureg.h
76
#define CIU_PP_DBG UINT64_C(0x0001070000000708)
sys/arch/mips/cavium/dev/octeon_ciureg.h
77
#define CIU_GSTOP UINT64_C(0x0001070000000710)
sys/arch/mips/cavium/dev/octeon_ciureg.h
78
#define CIU_NMI UINT64_C(0x0001070000000718)
sys/arch/mips/cavium/dev/octeon_ciureg.h
79
#define CIU_DINT UINT64_C(0x0001070000000720)
sys/arch/mips/cavium/dev/octeon_ciureg.h
80
#define CIU_FUSE UINT64_C(0x0001070000000728)
sys/arch/mips/cavium/dev/octeon_ciureg.h
81
#define CIU_BIST UINT64_C(0x0001070000000730)
sys/arch/mips/cavium/dev/octeon_ciureg.h
82
#define CIU_SOFT_BIST UINT64_C(0x0001070000000738)
sys/arch/mips/cavium/dev/octeon_ciureg.h
83
#define CIU_SOFT_RST UINT64_C(0x0001070000000740)
sys/arch/mips/cavium/dev/octeon_ciureg.h
84
#define CIU_SOFT_PRST UINT64_C(0x0001070000000748)
sys/arch/mips/cavium/dev/octeon_ciureg.h
85
#define CIU_PCI_INTA UINT64_C(0x0001070000000750)
sys/arch/mips/cavium/dev/octeon_ciureg.h
86
#define CIU_INT4_SUM0 UINT64_C(0x0001070000000c00)
sys/arch/mips/cavium/dev/octeon_ciureg.h
87
#define CIU_INT4_SUM1 UINT64_C(0x0001070000000c08)
sys/arch/mips/cavium/dev/octeon_ciureg.h
89
#define CIU_INT4_EN00 UINT64_C(0x0001070000000c80)
sys/arch/mips/cavium/dev/octeon_ciureg.h
90
#define CIU_INT4_EN01 UINT64_C(0x0001070000000c88)
sys/arch/mips/cavium/dev/octeon_ciureg.h
91
#define CIU_INT4_EN10 UINT64_C(0x0001070000000c90)
sys/arch/mips/cavium/dev/octeon_ciureg.h
92
#define CIU_INT4_EN11 UINT64_C(0x0001070000000c98)
sys/arch/mips/cavium/dev/octeon_ciureg.h
96
#define CIU_BASE UINT64_C(0x0001070000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
100
#define CP0_CVMCTL_TLBBRFTDIS UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
101
#define CP0_CVMCTL_FUSE_STARTBIT UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
102
#define CP0_CVMCTL_XXX_30 UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
103
#define CP0_CVMCTL_KASUMI UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
104
#define CP0_CVMCTL_NODFA_CP21 UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
105
#define CP0_CVMCTL_NOMUL UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
106
#define CP0_CVMCTL_NOCRYPTO UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
107
#define CP0_CVMCTL_RST_SHT UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
108
#define CP0_CVMCTL_BIST_DIS UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
109
#define CP0_CVMCTL_DISSETPRED UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_corereg.h
110
#define CP0_CVMCTL_DISJRPRED UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_corereg.h
111
#define CP0_CVMCTL_DISICACHE UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_corereg.h
112
#define CP0_CVMCTL_DISWAIT UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_corereg.h
113
#define CP0_CVMCTL_DEFET UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_corereg.h
114
#define CP0_CVMCTL_DISCO UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_corereg.h
115
#define CP0_CVMCTL_DISCE UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_corereg.h
116
#define CP0_CVMCTL_DDCLK UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_corereg.h
117
#define CP0_CVMCTL_DCICLK UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_corereg.h
118
#define CP0_CVMCTL_REPUN UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_corereg.h
119
#define CP0_CVMCTL_IPREF UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_corereg.h
120
#define CP0_CVMCTL_USEUN UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_corereg.h
121
#define CP0_CVMCTL_DISIOCACHE UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_corereg.h
122
#define CP0_CVMCTL_IRAND UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_corereg.h
123
#define CP0_CVMCTL_IPPCI UINT64_C(0x0000000000000380)
sys/arch/mips/cavium/dev/octeon_corereg.h
124
#define CP0_CVMCTL_IPTI UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_corereg.h
125
#define CP0_CVMCTL_XXX_3_2 UINT64_C(0x000000000000000c)
sys/arch/mips/cavium/dev/octeon_corereg.h
126
#define CP0_CVMCTL_LE UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_corereg.h
127
#define CP0_CVMCTL_USELY UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
131
#define CP0_CVMMEMCTL_TLBBIST UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
132
#define CP0_CVMMEMCTL_L1CBIST UINT64_C(0x4000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
133
#define CP0_CVMMEMCTL_L1DBIST UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
134
#define CP0_CVMMEMCTL_DCMBIST UINT64_C(0x1000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
135
#define CP0_CVMMEMCTL_PTGBIST UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
136
#define CP0_CVMMEMCTL_WBFBIST UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
137
#define CP0_CVMMEMCTL_XXX_57_36 UINT64_C(0x03fffff000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
138
#define CP0_CVMMEMCTL_DISMARKWBLONGTO UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
139
#define CP0_CVMMEMCTL_DISMRGCLRWBTO UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
140
#define CP0_CVMMEMCTL_IOBDMASCRMSB UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
141
#define CP0_CVMMEMCTL_SYNCWSMARKED UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
142
#define CP0_CVMMEMCTL_DISSYNCWS UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
143
#define CP0_CVMMEMCTL_DISWBFST UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
144
#define CP0_CVMMEMCTL_XKMEMENAS UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
145
#define CP0_CVMMEMCTL_XKMEMENAU UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
146
#define CP0_CVMMEMCTL_XKIOENAS UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
147
#define CP0_CVMMEMCTL_XKIOENAU UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
148
#define CP0_CVMMEMCTL_ALLSYNCW UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
149
#define CP0_CVMMEMCTL_NOMERGE UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_corereg.h
150
#define CP0_CVMMEMCTL_DIDTTO UINT64_C(0x0000000000600000)
sys/arch/mips/cavium/dev/octeon_corereg.h
151
#define CP0_CVMMEMCTL_CSRCLKALWYS UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_corereg.h
152
#define CP0_CVMMEMCTL_MCLKALWYS UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_corereg.h
153
#define CP0_CVMMEMCTL_WBFLTIME UINT64_C(0x0000000000070000)
sys/arch/mips/cavium/dev/octeon_corereg.h
154
#define CP0_CVMMEMCTL_ISTRNOL2 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_corereg.h
155
#define CP0_CVMMEMCTL_WBTHRESH UINT64_C(0x0000000000007800)
sys/arch/mips/cavium/dev/octeon_corereg.h
156
#define CP0_CVMMEMCTL_XXX_10_9 UINT64_C(0x0000000000000600)
sys/arch/mips/cavium/dev/octeon_corereg.h
157
#define CP0_CVMMEMCTL_CVMSEGENAK UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_corereg.h
158
#define CP0_CVMMEMCTL_CVMSEGENAS UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_corereg.h
159
#define CP0_CVMMEMCTL_CVMSEGENAU UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_corereg.h
160
#define CP0_CVMMEMCTL_LMEMSZ UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_corereg.h
166
#define CP0_MCD_XXX_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_corereg.h
167
#define CP0_MCD_DEXCC UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_corereg.h
168
#define CP0_MCD_CGSTP UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_corereg.h
169
#define CP0_MCD_CVGSTP UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_corereg.h
170
#define CP0_MCD_CVDM UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_corereg.h
171
#define CP0_MCD_GSDB UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_corereg.h
172
#define CP0_MCD_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_corereg.h
173
#define CP0_MCD_MSKM2 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_corereg.h
174
#define CP0_MCD_MSKM1 UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_corereg.h
175
#define CP0_MCD_MMC0 UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_corereg.h
176
#define CP0_MCD_XXX_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_corereg.h
177
#define CP0_MCD_PLS2 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_corereg.h
178
#define CP0_MCD_PLS1 UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_corereg.h
179
#define CP0_MCD_PLS0 UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_corereg.h
180
#define CP0_MCD_XXX_3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_corereg.h
181
#define CP0_MCD_MCD2 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_corereg.h
182
#define CP0_MCD_MCD1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_corereg.h
183
#define CP0_MCD_MCD0 UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
40
#define CP0_CACHEERRI_XXX_63_55 UINT64_C(0xff80000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
41
#define CP0_CACHEERRI_BADCOLF UINT64_C(0x007f000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
42
#define CP0_CACHEERRI_XXX_47 UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
43
#define CP0_CACHEERRI_BADCOL UINT64_C(0x00007f0000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
44
#define CP0_CACHEERRI_XXX_39_37 UINT64_C(0x000000e000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
45
#define CP0_CACHEERRI_LRUFAIL UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
46
#define CP0_CACHEERRI_AESFAIL UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
47
#define CP0_CACHEERRI_HSHFAIL UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
48
#define CP0_CACHEERRI_BHTBROKE UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
49
#define CP0_CACHEERRI_ICBROKE UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
50
#define CP0_CACHEERRI_XXX_31_15 UINT64_C(0x00000000ffff8000)
sys/arch/mips/cavium/dev/octeon_corereg.h
51
#define CP0_CACHEERRI_QW UINT64_C(0x0000000000006000)
sys/arch/mips/cavium/dev/octeon_corereg.h
52
#define CP0_CACHEERRI_ROW UINT64_C(0x0000000000001800)
sys/arch/mips/cavium/dev/octeon_corereg.h
53
#define CP0_CACHEERRI_SET UINT64_C(0x00000000000007e0)
sys/arch/mips/cavium/dev/octeon_corereg.h
54
#define CP0_CACHEERRI_WAY UINT64_C(0x0000000000000018)
sys/arch/mips/cavium/dev/octeon_corereg.h
55
#define CP0_CACHEERRI_XXX_2_1 UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_corereg.h
56
#define CP0_CACHEERRI_DPERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
60
#define CP0_CACHEERRD_XXX_63_13 UINT64_C(0xffffffffffffe000)
sys/arch/mips/cavium/dev/octeon_corereg.h
61
#define CP0_CACHEERRD_SET UINT64_C(0x0000000000001f80)
sys/arch/mips/cavium/dev/octeon_corereg.h
62
#define CP0_CACHEERRD_VA63 UINT64_C(0x0000000000000078)
sys/arch/mips/cavium/dev/octeon_corereg.h
63
#define CP0_CACHEERRD_XXX_2_1 UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_corereg.h
64
#define CP0_CACHEERRD_PERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
68
#define CP0_TAGLOI_R UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
69
#define CP0_TAGLOI_XXX_61_60 UINT64_C(0x3000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
70
#define CP0_TAGLOI_ASID UINT64_C(0x0f00000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
71
#define CP0_TAGLOI_XXX_51_49 UINT64_C(0x00f0000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
72
#define CP0_TAGLOI_TAG UINT64_C(0x000fffffffffe000)
sys/arch/mips/cavium/dev/octeon_corereg.h
73
#define CP0_TAGLOI_INDEX UINT64_C(0x0000000000001f80)
sys/arch/mips/cavium/dev/octeon_corereg.h
74
#define CP0_TAGLOI_XXX_6_2 UINT64_C(0x000000000000007c)
sys/arch/mips/cavium/dev/octeon_corereg.h
75
#define CP0_TAGLOI_G UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_corereg.h
76
#define CP0_TAGLOI_VALID UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
80
#define CP0_TAGLOD_R UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
81
#define CP0_TAGLOD_XXX_61_60 UINT64_C(0x3000000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
82
#define CP0_TAGLOD_ASID UINT64_C(0x0f00000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
83
#define CP0_TAGLOD_XXX_51_49 UINT64_C(0x00f0000000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
84
#define CP0_TAGLOD_TAG UINT64_C(0x000fffffffffff80)
sys/arch/mips/cavium/dev/octeon_corereg.h
85
#define CP0_TAGLOD_XXX_6_2 UINT64_C(0x000000000000007c)
sys/arch/mips/cavium/dev/octeon_corereg.h
86
#define CP0_TAGLOD_G UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_corereg.h
87
#define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_corereg.h
92
#define CP0_CVMCTL_XXX_63_43 UINT64_C(0xfffff80000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
93
#define CP0_CVMCTL_STEPRATE UINT64_C(0x0000078000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
94
#define CP0_CVMCTL_ZUC UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
95
#define CP0_CVMCTL_CAMELLIA UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
96
#define CP0_CVMCTL_USEMAK UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
97
#define CP0_CVMCTL_SMS4 UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
98
#define CP0_CVMCTL_DISABLEPAUSE UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_corereg.h
99
#define CP0_CVMCTL_SNOW3G UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
100
#define FPA_INT_ENB_Q6_COFF UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
101
#define FPA_INT_ENB_Q6_UND UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
102
#define FPA_INT_ENB_Q5_PERR UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
103
#define FPA_INT_ENB_Q5_COFF UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
104
#define FPA_INT_ENB_Q5_UND UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
105
#define FPA_INT_ENB_Q4_PERR UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
106
#define FPA_INT_ENB_Q4_COFF UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
107
#define FPA_INT_ENB_Q4_UND UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
108
#define FPA_INT_ENB_Q3_PERR UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
109
#define FPA_INT_ENB_Q3_COFF UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
110
#define FPA_INT_ENB_Q3_UND UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
111
#define FPA_INT_ENB_Q2_PERR UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
112
#define FPA_INT_ENB_Q2_COFF UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_fpareg.h
113
#define FPA_INT_ENB_Q2_UND UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_fpareg.h
114
#define FPA_INT_ENB_Q1_PERR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_fpareg.h
115
#define FPA_INT_ENB_Q1_COFF UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_fpareg.h
116
#define FPA_INT_ENB_Q1_UND UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_fpareg.h
117
#define FPA_INT_ENB_Q0_PERR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_fpareg.h
118
#define FPA_INT_ENB_Q0_COFF UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_fpareg.h
119
#define FPA_INT_ENB_Q0_UND UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_fpareg.h
120
#define FPA_INT_ENB_FED1_DBE UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_fpareg.h
121
#define FPA_INT_ENB_FED1_SBE UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_fpareg.h
122
#define FPA_INT_ENB_FED0_DBE UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_fpareg.h
123
#define FPA_INT_ENB_FED0_SBE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_fpareg.h
125
#define FPA_CTL_STATUS_XXX_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
126
#define FPA_CTL_STATUS_RESET UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
127
#define FPA_CTL_STATUS_USE_LDT UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
128
#define FPA_CTL_STATUS_USE_STT UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
129
#define FPA_CTL_STATUS_ENB UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
130
#define FPA_CTL_STATUS_MEM1_ERR UINT64_C(0x0000000000003f80)
sys/arch/mips/cavium/dev/octeon_fpareg.h
131
#define FPA_CTL_STATUS_MEM0_ERR UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_fpareg.h
133
#define FPA_QUEX_AVAILABLE_XXX_63_29 UINT64_C(0xffffffffe0000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
134
#define FPA_QUEX_AVAILABLE_QUE_SIZ UINT64_C(0x000000001fffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
136
#define FPA_WART_CTL_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
137
#define FPA_WART_CTL_CTL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
139
#define FPA_WART_STATUS_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
140
#define FPA_WART_STATUS_STATUS UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
142
#define FPA_BIST_STATUS_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_fpareg.h
143
#define FPA_BIST_STATUS_FRD UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_fpareg.h
144
#define FPA_BIST_STATUS_FPF0 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_fpareg.h
145
#define FPA_BIST_STATUS_FPF1 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_fpareg.h
146
#define FPA_BIST_STATUS_FFR UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_fpareg.h
147
#define FPA_BIST_STATUS_FDR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_fpareg.h
149
#define FPA_QUEX_PAGE_INDEX_XXX_63_25 UINT64_C(0xfffffffffe000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
150
#define FPA_QUEX_PAGE_INDEX_PG_NUM UINT64_C(0x0000000001ffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
152
#define FPA_QUE_EXP_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
153
#define FPA_QUE_EXP_XXX_31_29 UINT64_C(0x00000000e0000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
154
#define FPA_QUE_EXP_EXP_QUE UINT64_C(0x000000001c000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
155
#define FPA_QUE_EXP_EXP_INDX UINT64_C(0x0000000003ffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
157
#define FPA_QUE_ACT_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
158
#define FPA_QUE_ACT_XXX_31_29 UINT64_C(0x00000000e0000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
159
#define FPA_QUE_ACT_ACT_QUE UINT64_C(0x000000001c000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
160
#define FPA_QUE_ACT_ACT_INDX UINT64_C(0x0000000003ffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
171
#define FPA_OPS_STORE_ADDR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
173
#define FPA_OPS_STORE_DATA_DWBCOUNT UINT64_C(0x00000000000001ff)
sys/arch/mips/cavium/dev/octeon_fpareg.h
65
#define FPA_INT_SUM_XXX_63_28 UINT64_C(0xfffffffff0000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
66
#define FPA_INT_SUM_Q7_PERR UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
67
#define FPA_INT_SUM_Q7_COFF UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
68
#define FPA_INT_SUM_Q7_UND UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
69
#define FPA_INT_SUM_Q6_PERR UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
70
#define FPA_INT_SUM_Q6_COFF UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
71
#define FPA_INT_SUM_Q6_UND UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
72
#define FPA_INT_SUM_Q5_PERR UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
73
#define FPA_INT_SUM_Q5_COFF UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
74
#define FPA_INT_SUM_Q5_UND UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
75
#define FPA_INT_SUM_Q4_PERR UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
76
#define FPA_INT_SUM_Q4_COFF UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
77
#define FPA_INT_SUM_Q4_UND UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
78
#define FPA_INT_SUM_Q3_PERR UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
79
#define FPA_INT_SUM_Q3_COFF UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
80
#define FPA_INT_SUM_Q3_UND UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
81
#define FPA_INT_SUM_Q2_PERR UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
82
#define FPA_INT_SUM_Q2_COFF UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_fpareg.h
83
#define FPA_INT_SUM_Q2_UND UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_fpareg.h
84
#define FPA_INT_SUM_Q1_PERR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_fpareg.h
85
#define FPA_INT_SUM_Q1_COFF UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_fpareg.h
86
#define FPA_INT_SUM_Q1_UND UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_fpareg.h
87
#define FPA_INT_SUM_Q0_PERR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_fpareg.h
88
#define FPA_INT_SUM_Q0_COFF UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_fpareg.h
89
#define FPA_INT_SUM_Q0_UND UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_fpareg.h
90
#define FPA_INT_SUM_FED1_DBE UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_fpareg.h
91
#define FPA_INT_SUM_FED1_SBE UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_fpareg.h
92
#define FPA_INT_SUM_FED0_DBE UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_fpareg.h
93
#define FPA_INT_SUM_FED0_SBE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_fpareg.h
95
#define FPA_INT_ENB_XXX_63_28 UINT64_C(0xfffffffff0000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
96
#define FPA_INT_ENB_Q7_PERR UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
97
#define FPA_INT_ENB_Q7_COFF UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
98
#define FPA_INT_ENB_Q7_UND UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_fpareg.h
99
#define FPA_INT_ENB_Q6_PERR UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
126
#define RXN_INT_REG_XXX_63_19 UINT64_C(0xfffffffffff80000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
127
#define RXN_INT_REG_PHY_DUPX UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
128
#define RXN_INT_REG_PHY_SPD UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
129
#define RXN_INT_REG_PHY_LINK UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
130
#define RXN_INT_REG_IFGERR UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
131
#define RXN_INT_REG_COLDET UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
132
#define RXN_INT_REG_FALERR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
133
#define RXN_INT_REG_RSVERR UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
134
#define RXN_INT_REG_PCTERR UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
135
#define RXN_INT_REG_OVRERR UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
136
#define RXN_INT_REG_NIBERR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
137
#define RXN_INT_REG_SKPERR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
138
#define RXN_INT_REG_RCVERR UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
139
#define RXN_INT_REG_LENERR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
140
#define RXN_INT_REG_ALNERR UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
141
#define RXN_INT_REG_FCSERR UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
142
#define RXN_INT_REG_JABBER UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
143
#define RXN_INT_REG_MAXERR UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
144
#define RXN_INT_REG_CAREXT UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
145
#define RXN_INT_REG_MINERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
149
#define RXN_INT_EN_XXX_63_19 UINT64_C(0xfffffffffff80000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
150
#define RXN_INT_EN_PHY_DUPX UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
151
#define RXN_INT_EN_PHY_SPD UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
152
#define RXN_INT_EN_PHY_LINK UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
153
#define RXN_INT_EN_IFGERR UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
154
#define RXN_INT_EN_COLDET UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
155
#define RXN_INT_EN_FALERR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
156
#define RXN_INT_EN_RSVERR UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
157
#define RXN_INT_EN_PCTERR UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
158
#define RXN_INT_EN_OVRERR UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
159
#define RXN_INT_EN_NIBERR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
160
#define RXN_INT_EN_SKPERR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
161
#define RXN_INT_EN_RCVERR UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
162
#define RXN_INT_EN_LENERR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
163
#define RXN_INT_EN_ALNERR UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
164
#define RXN_INT_EN_FCSERR UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
165
#define RXN_INT_EN_JABBER UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
166
#define RXN_INT_EN_MAXERR UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
167
#define RXN_INT_EN_CAREXT UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
168
#define RXN_INT_EN_MINERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
172
#define PRTN_CFG_XXX_63_9 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
173
#define PRTN_CFG_SPEED_MSB UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
174
#define PRTN_CFG_XXX_7_4 UINT64_C(0x00000000000000f0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
175
#define PRTN_CFG_SLOTTIME UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
176
#define PRTN_CFG_DUPLEX UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
177
#define PRTN_CFG_SPEED UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
178
#define PRTN_CFG_EN UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
182
#define RXN_FRM_CTL_XXX_63_11 UINT64_C(0xfffffffffffff800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
183
#define RXN_FRM_CTL_NULL_DIS UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
184
#define RXN_FRM_CTL_PRE_ALIGN UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
185
#define RXN_FRM_CTL_PAD_LEN UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
186
#define RXN_FRM_CTL_VLAN_LEN UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
187
#define RXN_FRM_CTL_PRE_FREE UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
188
#define RXN_FRM_CTL_CTL_SMAC UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
189
#define RXN_FRM_CTL_CTL_MCST UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
190
#define RXN_FRM_CTL_CTL_BCK UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
191
#define RXN_FRM_CTL_CTL_DRP UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
192
#define RXN_FRM_CTL_PRE_STRP UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
193
#define RXN_FRM_CTL_PRE_CHK UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
197
#define RXN_FRM_CKK_XXX_63_10 UINT64_C(0xfffffffffffffc00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
198
#define RXN_FRM_CHK_NIBERR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
199
#define RXN_FRM_CHK_SKPERR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
200
#define RXN_FRM_CHK_RCVERR UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
201
#define RXN_FRM_CHK_LENERR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
202
#define RXN_FRM_CHK_ALNERR UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
203
#define RXN_FRM_CHK_FCSERR UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
204
#define RXN_FRM_CHK_JABBER UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
205
#define RXN_FRM_CHK_MAXERR UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
206
#define RXN_FRM_CHK_CAREXT UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
207
#define RXN_FRM_CHK_MINERR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
211
#define RXN_RRM_MIN_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
212
#define RXN_RRM_MIN_LEN UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
216
#define RXN_RRM_MAX_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
217
#define RXN_RRM_MAX_LEN UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
221
#define RXN_JABBER_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
222
#define RXN_JABBER_CNT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
226
#define RXN_DECISION_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
227
#define RXN_DECISION_CNT UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
231
#define RXN_UDD_SKP_XXX_63_9 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
232
#define RXN_UDD_SKP_FCSSEL UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
233
#define RXN_UDD_SKP_XXX_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
234
#define RXN_UDD_SKP_LEN UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
238
#define RXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
239
#define RXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
243
#define RXN_IFG_XXX_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
244
#define RXN_IFG_IFG UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
248
#define RXN_RX_INBND_XXX_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
249
#define RXN_RX_INBND_DUPLEX UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
252
#define RXN_RX_INBND_SPEED UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
257
#define RXN_RX_INBND_STATUS UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
261
#define RXN_STATS_PKTS_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
262
#define RXN_STATS_PKTS_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
266
#define RXN_STATS_OCTS_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
267
#define RXN_STATS_OCTS_CNT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
271
#define RXN_STATS_PKTS_CTL_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
272
#define RXN_STATS_PKTS_CTL_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
276
#define RXN_STATS_OCTS_CTL_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
277
#define RXN_STATS_OCTS_CTL_CNT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
281
#define RXN_STATS_PKTS_DMAC_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
282
#define RXN_STATS_PKTS_DMAC_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
286
#define RXN_STATS_OCTS_DMAC_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
287
#define RXN_STATS_OCTS_DMAC_CNT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
291
#define RXN_STATS_PKTS_DRP_XXX_63_48 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
292
#define RXN_STATS_PKTS_DRP_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
296
#define RXN_STATS_OCTS_DRP_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
297
#define RXN_STATS_OCTS_DRP_CNT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
301
#define RXN_STATS_PKTS_BAD_XXX_63_48 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
302
#define RXN_STATS_PKTS_BAD_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
306
#define RXN_ADR_CTL_XXX_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
307
#define RXN_ADR_CTL_CAM_MODE UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
310
#define RXN_ADR_CTL_MCST UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
315
#define RXN_ADR_CTL_BCST UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
319
#define RXN_ADR_CAM_EN_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
320
#define RXN_ADR_CAM_EN_EN UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
323
#define RXN_ADR_CAMN_ADR UINT64_C(0xffffffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
327
#define TXN_CLK_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
328
#define TXN_CLK_CLK_CNT UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
332
#define TXN_THRESH_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
333
#define TXN_THRESH_CNT UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
337
#define TXN_APPEND_XXX_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
338
#define TXN_APPEND_FORCE_FCS UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
339
#define TXN_APPEND_FCS UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
340
#define TXN_APPEND_PAD UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
341
#define TXN_APPEND_PREAMBLE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
345
#define TXN_SLOT_XXX_63_10 UINT64_C(0xfffffffffffffc00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
346
#define TXN_SLOT_SLOT UINT64_C(0x00000000000003ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
350
#define TXN_BURST_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
351
#define TXN_BURST_BURST UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
355
#define SMACN_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
356
#define SMACN_SMAC UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
360
#define TXN_PAUSE_PKT_TIME_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
361
#define TXN_PAUSE_PKT_TIME_TIME UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
365
#define TXN_MIN_PKT_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
366
#define TXN_MIN_PKT_MIN_SIZE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
370
#define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
371
#define TXN_PAUSE_PKT_INTERVAL_INTERVAL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
375
#define TXN_SOFT_PAUSE_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
376
#define TXN_SOFT_PAUSE_TIME UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
380
#define TXN_PAUSE_TOGO_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
381
#define TXN_PAUSE_TOGO_TIME UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
385
#define TXN_PAUSE_ZERO_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
386
#define TXN_PAUSE_ZERO_SEND UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
390
#define TXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
391
#define TXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
395
#define TXN_CTL_XXX_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
396
#define TXN_CTL_XSDEF_EN UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
397
#define TXN_CTL_XSCOL_EN UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
401
#define TXN_STAT0_XSDEF UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
402
#define TXN_STAT0_XSCOL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
406
#define TXN_STAT1_SCOL UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
407
#define TXN_STAT1_MSCOL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
411
#define TXN_STAT2_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
412
#define TXN_STAT2_OCTS UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
416
#define TXN_STAT3_XXX_63_48 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
417
#define TXN_STAT3_PKTS UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
421
#define TXN_STAT4_HIST1 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
422
#define TXN_STAT4_HIST0 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
426
#define TXN_STAT5_HIST3 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
427
#define TXN_STAT5_HIST2 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
431
#define TXN_STAT6_HIST5 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
432
#define TXN_STAT6_HIST4 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
436
#define TXN_STAT7_HIST7 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
437
#define TXN_STAT7_HIST6 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
441
#define TXN_STAT8_MCST UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
442
#define TXN_STAT8_BCST UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
446
#define TXN_STAT9_UNDFLW UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
447
#define TXN_STAT9_CTL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
451
#define BIST_XXX_63_10 UINT64_C(0xfffffffffffffc00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
452
#define BIST_STATUS UINT64_C(0x00000000000003ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
456
#define RX_PRTS_XXX_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
457
#define RX_PRTS_PRTS UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
461
#define RX_BP_DROPN_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
462
#define RX_BP_DROPN_MARK UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
466
#define RX_BP_ONN_XXX_63_9 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
467
#define RX_BP_ONN_MARK UINT64_C(0x00000000000001ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
471
#define RX_BP_OFFN_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
472
#define RX_BP_OFFN_MARK UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
476
#define TX_PRTS_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
477
#define TX_PRTS_PRTS UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
481
#define TX_IFG_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
482
#define TX_IFG_IFG2 UINT64_C(0x00000000000000f0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
483
#define TX_IFG_IFG1 UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
487
#define TX_JAM_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
488
#define TX_JAM_JAM UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
492
#define TX_COL_ATTEMPT_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
493
#define TX_COL_ATTEMPT_LIMIT UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
497
#define TX_PAUSE_PKT_DMAC_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
498
#define TX_PAUSE_PKT_DMAC_DMAC UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
502
#define TX_PAUSE_PKT_TYPE_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
503
#define TX_PAUSE_PKT_TYPE_TYPE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
507
#define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
508
#define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
509
#define TX_OVR_BP_EN UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
510
#define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
511
#define TX_OVR_BP_BP UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
512
#define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
513
#define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
517
#define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
518
#define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
519
#define TX_OVR_BP_EN UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
520
#define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
521
#define TX_OVR_BP_BP UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
522
#define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
523
#define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
527
#define TX_BP_SR_XXX_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
528
#define TX_BP_SR_BP UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
532
#define TX_CORRUPT_XXX_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
533
#define TX_CORRUPT_CORRUPT UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
537
#define RX_PRT_INFO_XXX_63_19 UINT64_C(0xfffffffffff80000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
538
#define RX_PRT_INFO_DROP UINT64_C(0x0000000000070000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
539
#define RX_PRT_INFO_XXX_15_3 UINT64_C(0x000000000000fff8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
540
#define RX_PRT_INFO_COMMIT UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
544
#define TX_LFSR_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
545
#define TX_LFSR_LFSR UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
549
#define TX_INT_REG_XXX_63_20 UINT64_C(0xfffffffffff00000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
550
#define TX_INT_REG_XXX_19 UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
551
#define TX_INT_REG_LATE_COL UINT64_C(0x0000000000070000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
552
#define TX_INT_REG_XXX_15 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
553
#define TX_INT_REG_XSDEF UINT64_C(0x0000000000007000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
554
#define TX_INT_REG_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
555
#define TX_INT_REG_XSCOL UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
556
#define TX_INT_REG_XXX_7_5 UINT64_C(0x00000000000000e0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
557
#define TX_INT_REG_UNDFLW UINT64_C(0x000000000000001c)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
558
#define TX_INT_REG_XXX_1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
559
#define TX_INT_REG_PKO_NXA UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
563
#define TX_INT_EN_XXX_63_20 UINT64_C(0xfffffffffff00000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
564
#define TX_INT_EN_XXX_19 UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
565
#define TX_INT_EN_LATE_COL UINT64_C(0x0000000000070000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
566
#define TX_INT_EN_XXX_15 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
567
#define TX_INT_EN_XSDEF UINT64_C(0x0000000000007000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
568
#define TX_INT_EN_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
569
#define TX_INT_EN_XSCOL UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
570
#define TX_INT_EN_XXX_7_5 UINT64_C(0x00000000000000e0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
571
#define TX_INT_EN_UNDFLW UINT64_C(0x000000000000001c)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
572
#define TX_INT_EN_XXX_1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
573
#define TX_INT_EN_PKO_NXA UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
577
#define NXA_ADR_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
578
#define NXA_ADR_PRT UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
582
#define BAD_REG_XXX_63_31 UINT64_C(0xffffffff80000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
583
#define BAD_REG_INB_NXA UINT64_C(0x0000000078000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
584
#define BAD_REG_STATOVR UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
585
#define BAD_REG_XXX_25 UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
586
#define BAD_REG_LOSTSTAT UINT64_C(0x0000000001c00000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
587
#define BAD_REG_XXX_21_18 UINT64_C(0x00000000003c0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
588
#define BAD_REG_XXX_17_5 UINT64_C(0x000000000003ffe0)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
589
#define BAD_REG_OUT_OVR UINT64_C(0x000000000000001c)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
590
#define BAD_REG_XXX_1_0 UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
594
#define STAT_BP_XXX_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
595
#define STAT_BP_BP UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
596
#define STAT_BP_CNT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
600
#define TX_CLK_MSKN_XXX_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
601
#define TX_CLK_MSKN_MSK UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
605
#define RX_TX_STATUS_XXX_63_7 UINT64_C(0xffffffffffffff80)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
606
#define RX_TX_STATUS_TX UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
607
#define RX_TX_STATUS_XXX_3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
608
#define RX_TX_STATUS_RX UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
612
#define INF_MODE_XXX_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
613
#define INF_MODE_P0MII UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
614
#define INF_MODE_EN UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
615
#define INF_MODE_TYPE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
617
#define INF_MODE_MODE UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
618
#define INF_MODE_MODE_SGMII UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
619
#define INF_MODE_MODE_XAUI UINT64_C(0x0000000000000030)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
621
#define MIO_QLM_CFG(x) (UINT64_C(0x0001180000001590) + (x)*8)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
623
#define MIO_QLM_CFG_CFG UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
637
#define GMX0_BASE_PORT0 UINT64_C(0x0001180008000000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
649
#define PCS_BASE(g, i) (UINT64_C(0x00011800b0001000) + 0x8000000 * (g) + 0x400 * (i))
sys/arch/mips/cavium/dev/octeon_gmxreg.h
657
#define PCS_MR_CONTROL_RES_16_63 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
658
#define PCS_MR_CONTROL_RESET UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
659
#define PCS_MR_CONTROL_LOOPBCK1 UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
660
#define PCS_MR_CONTROL_SPDLSB UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
661
#define PCS_MR_CONTROL_AN_EN UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
662
#define PCS_MR_CONTROL_PWR_DN UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
663
#define PCS_MR_CONTROL_RES_10_10 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
664
#define PCS_MR_CONTROL_RST_AN UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
665
#define PCS_MR_CONTROL_DUPLEX UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
666
#define PCS_MR_CONTROL_COLTST UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
667
#define PCS_MR_CONTROL_SPDMSB UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
668
#define PCS_MR_CONTROL_UNI UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
669
#define PCS_MR_CONTROL_RES_0_4 UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
671
#define PCS_MR_STATUS_RES_16_63 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
672
#define PCS_MR_STATUS_HUN_T4 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
673
#define PCS_MR_STATUS_HUN_XFD UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
674
#define PCS_MR_STATUS_HUN_XHD UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
675
#define PCS_MR_STATUS_TEN_FD UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
676
#define PCS_MR_STATUS_TEN_HD UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
677
#define PCS_MR_STATUS_HUN_T2FD UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
678
#define PCS_MR_STATUS_HUN_T2HD UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
679
#define PCS_MR_STATUS_EXT_ST UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
680
#define PCS_MR_STATUS_RES_7_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
681
#define PCS_MR_STATUS_PRB_SUP UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
682
#define PCS_MR_STATUS_AN_CPT UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
683
#define PCS_MR_STATUS_RM_FLT UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
684
#define PCS_MR_STATUS_AN_ABIL UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
685
#define PCS_MR_STATUS_LNK_ST UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
686
#define PCS_MR_STATUS_RES_1_1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
687
#define PCS_MR_STATUS_EXTND UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
689
#define PCS_LINK_TIMER_COUNT_MASK UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
691
#define PCS_MISC_CTL_SGMII UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
692
#define PCS_MISC_CTL_GMXENO UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
693
#define PCS_MISC_CTL_LOOPBCK2 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
694
#define PCS_MISC_CTL_MAC_PHY UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
695
#define PCS_MISC_CTL_MODE UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
696
#define PCS_MISC_CTL_AN_OVRD UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_gmxreg.h
697
#define PCS_MISC_CTL_SAMP_PT UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
68
#define GPIO_BIT_CFG_OUT_SEL UINT64_C(0x00000000001f0000)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
69
#define GPIO_BIT_CFG_XXX_63_12 UINT64_C(0xfffffffffffff000)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
70
#define GPIO_BIT_CFG_FIL_SEL UINT64_C(0x0000000000000f00)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
71
#define GPIO_BIT_CFG_FIL_CNT UINT64_C(0x00000000000000f0)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
72
#define GPIO_BIT_CFG_INT_TYPE UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
73
#define GPIO_BIT_CFG_INT_EN UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
74
#define GPIO_BIT_CFG_RX_XOR UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_gpioreg.h
75
#define GPIO_BIT_CFG_TX_OE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
143
#define IPD_WQE_WORD2_RAW_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
144
#define IPD_WQE_WORD2_RAW_WORD UINT64_C(0x00ffffffffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
147
#define IPD_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
148
#define IPD_WQE_WORD2_IP_IPOFF UINT64_C(0x00ff000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
149
#define IPD_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
150
#define IPD_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
151
#define IPD_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
152
#define IPD_WQE_WORD2_IP_VC UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
153
#define IPD_WQE_WORD2_IP_VLANID UINT64_C(0x00000fff00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
154
#define IPD_WQE_WORD2_IP_31_20 UINT64_C(0x00000000fff00000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
155
#define IPD_WQE_WORD2_IP_CO UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
156
#define IPD_WQE_WORD2_IP_TU UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
157
#define IPD_WQE_WORD2_IP_SE UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
158
#define IPD_WQE_WORD2_IP_V6 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
159
#define IPD_WQE_WORD2_IP_15 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
160
#define IPD_WQE_WORD2_IP_LE UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
161
#define IPD_WQE_WORD2_IP_FR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
162
#define IPD_WQE_WORD2_IP_IE UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
163
#define IPD_WQE_WORD2_IP_B UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
164
#define IPD_WQE_WORD2_IP_M UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
165
#define IPD_WQE_WORD2_IP_NI UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
166
#define IPD_WQE_WORD2_IP_RE UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
167
#define IPD_WQE_WORD2_IP_OPCODE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
170
#define IPD_WQE_WORD2_OTH_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
171
#define IPD_WQE_WORD2_OTH_55_48 UINT64_C(0x00ff000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
172
#define IPD_WQE_WORD2_OTH_VV UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
173
#define IPD_WQE_WORD2_OTH_VS UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
174
#define IPD_WQE_WORD2_OTH_45 UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
175
#define IPD_WQE_WORD2_OTH_VC UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
176
#define IPD_WQE_WORD2_OTH_VLANID UINT64_C(0x00000fff00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
177
#define IPD_WQE_WORD2_OTH_31_14 UINT64_C(0x00000000ffffc000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
178
#define IPD_WQE_WORD2_OTH_IR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
179
#define IPD_WQE_WORD2_OTH_IA UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
180
#define IPD_WQE_WORD2_OTH_B UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
181
#define IPD_WQE_WORD2_OTH_M UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
182
#define IPD_WQE_WORD2_OTH_NI UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
183
#define IPD_WQE_WORD2_OTH_RE UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
184
#define IPD_WQE_WORD2_OTH_OPCODE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
189
#define IPD_WQE_WORD3_63 UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
190
#define IPD_WQE_WORD3_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
191
#define IPD_WQE_WORD3_58_56 UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
192
#define IPD_WQE_WORD3_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
193
#define IPD_WQE_WORD3_ADDR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
198
#define IPD_1ST_MBUFF_SKIP_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
199
#define IPD_1ST_MBUFF_SKIP_SZ UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
204
#define IPD_NOT_1ST_MBUFF_SKIP_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
205
#define IPD_NOT_1ST_MBUFF_SKIP_SZ UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
210
#define IPD_PACKET_MBUFF_SIZE_63_12 UINT64_C(0xfffffffffffff000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
211
#define IPD_PACKET_MBUFF_SIZE_MB_SIZE UINT64_C(0x0000000000000fff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
216
#define IPD_CTL_STATUS_63_10 UINT64_C(0xfffffffffffffc00)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
217
#define IPD_CTL_STATUS_LEN_M8 UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
218
#define IPD_CTL_STATUS_RESET UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
219
#define IPD_CTL_STATUS_ADDPKT UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
220
#define IPD_CTL_STATUS_NADDBUF UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
221
#define IPD_CTL_STATUS_PKT_LEND UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
222
#define IPD_CTL_STATUS_WQE_LEND UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
223
#define IPD_CTL_STATUS_PBP_EN UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
224
#define IPD_CTL_STATUS_OPC_MODE UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
229
#define IPD_CTL_STATUS_IPD_EN UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
234
#define IPD_WQE_FPA_QUEUE_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
235
#define IPD_WQE_FPA_QUEUE_WQE_QUE UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
240
#define IPD_PORTN_BP_PAGE_CNT_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
241
#define IPD_PORTN_BP_PAGE_CNT_BP_ENB UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
242
#define IPD_PORTN_BP_PAGE_CNT_PAGE_CNT UINT64_C(0x000000000001ffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
247
#define IPD_SUB_PORT_BP_PAGE_CNT_63_18 UINT64_C(0xffffffff80000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
248
#define IPD_SUB_PORT_BP_PAGE_CNT_PORT UINT64_C(0x000000007e000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
249
#define IPD_SUB_PORT_BP_PAGE_CNT_PAGE_CNT UINT64_C(0x0000000001ffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
254
#define IPD_1ST_NEXT_PTR_BACK_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
255
#define IPD_1ST_NEXT_PTR_BACK_BACK UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
260
#define IPD_2ND_NEXT_PTR_BACK_63_4 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
261
#define IPD_2ND_NEXT_PTR_BACK_BACK UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
266
#define IPD_INT_ENB_63_4 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
267
#define IPD_INT_ENB_BP_SUB UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
268
#define IPD_INT_ENB_PRC_PAR3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
269
#define IPD_INT_ENB_PRC_PAR2 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
270
#define IPD_INT_ENB_PRC_PAR1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
271
#define IPD_INT_ENB_PRC_PAR0 UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
276
#define IPD_INT_SUM_63_4 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
277
#define IPD_INT_SUM_BP_SUB UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
278
#define IPD_INT_SUM_PRC_PAR3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
279
#define IPD_INT_SUM_PRC_PAR2 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
280
#define IPD_INT_SUM_PRC_PAR1 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
281
#define IPD_INT_SUM_PRC_PAR0 UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
286
#define IPD_SUB_PORT_FCS_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
287
#define IPD_SUB_PORT_FCS_PORT_BIT UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
292
#define IPD_QOSN_READ_MARKS_DROP UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
293
#define IPD_QOSN_READ_MARKS_PASS UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
298
#define IPD_PORT_BP_COUNTERS_PAIRN_63_25 UINT64_C(0xfffffffffe000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
299
#define IPD_PORT_BP_COUNTERS_PAIRN_CNT_VAL UINT64_C(0x0000000001ffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
304
#define IPD_RED_PORT_ENABLE_PRB_DLY UINT64_C(0xfffc000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
305
#define IPD_RED_PORT_ENABLE_AVG_DLY UINT64_C(0x0003fff000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
306
#define IPD_RED_PORT_ENABLE_PRT_ENB UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
311
#define IPD_RED_QUEN_PARAM_63_49 UINT64_C(0xfffe000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
312
#define IPD_RED_QUEN_PARAM_USE_PCNT UINT64_C(0x0001000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
313
#define IPD_RED_QUEN_PARAM_NEW_CON UINT64_C(0x0000ff0000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
314
#define IPD_RED_QUEN_PARAM_AVG_CON UINT64_C(0x000000ff00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
315
#define IPD_RED_QUEN_PARAM_PRB_CON UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
320
#define IPD_PTR_COUNT_63_19 UINT64_C(0xfffffffffff80000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
321
#define IPD_PTR_COUNT_PKTV_CNT UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
322
#define IPD_PTR_COUNT_WQEV_CNT UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
323
#define IPD_PTR_COUNT_PFIF_CNT UINT64_C(0x000000000001c000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
324
#define IPD_PTR_COUNT_PKT_PCNT UINT64_C(0x0000000000003f80)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
325
#define IPD_PTR_COUNT_WQE_PCNT UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
330
#define IPD_BP_PRT_RED_END_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
331
#define IPD_BP_PRT_RED_END_PRT_ENB UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
336
#define IPD_QUE0_FREE_PAGE_CNT_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
337
#define IPD_QUE0_FREE_PAGE_CNT_Q0_PCNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
342
#define IPD_CLK_COUNT_CLK_CNT UINT64_C(0xffffffffffffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
347
#define IPD_PWP_PTR_FIFO_CTL_63_61 UINT64_C(0xe000000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
348
#define IPD_PWP_PTR_FIFO_CTL_MAX_CNTS UINT64_C(0x1fc0000000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
349
#define IPD_PWP_PTR_FIFO_CTL_WRADDR UINT64_C(0x003fc00000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
350
#define IPD_PWP_PTR_FIFO_CTL_PRADDR UINT64_C(0x00003fc000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
351
#define IPD_PWP_PTR_FIFO_CTL_PTR UINT64_C(0x0000003ffffffe00)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
352
#define IPD_PWP_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
353
#define IPD_PWP_PTR_FIFO_CTL_RADDR UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
358
#define IPD_PRC_HOLD_PTR_FIFO_CTL_63_39 UINT64_C(0xffffff8000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
359
#define IPD_PRC_HOLD_PTR_FIFO_CTL_MAX_PTR UINT64_C(0x0000007000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
360
#define IPD_PRC_HOLD_PTR_FIFO_CTL_PRADDR UINT64_C(0x0000000e00000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
361
#define IPD_PRC_HOLD_PTR_FIFO_CTL_PTR UINT64_C(0x00000001fffffff0)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
362
#define IPD_PRC_HOLD_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
363
#define IPD_PRC_HOLD_PTR_FIFO_CTL_RADDR UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
368
#define IPD_PRC_PORT_PTR_FIFO_CTL_63_44 UINT64_C(0xfffff00000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
369
#define IPD_PRC_PORT_PTR_FIFO_CTL_MAX_PTR UINT64_C(0x00000fe000000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
370
#define IPD_PRC_PORT_PTR_FIFO_CTL_PTR UINT64_C(0x0000001fffffff00)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
371
#define IPD_PRC_PORT_PTR_FIFO_CTL_CENA UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
372
#define IPD_PRC_PORT_PTR_FIFO_CTL_RADDR UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
377
#define IPD_PKT_PTR_VALID_63_29 UINT64_C(0xffffffffe0000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
378
#define IPD_PKT_PTR_VALID_PTR UINT64_C(0x000000001fffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
383
#define IPD_WQE_PTR_VALID_63_29 UINT64_C(0xffffffffe0000000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
384
#define IPD_WQE_PTR_VALID_PTR UINT64_C(0x000000001fffffff)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
389
#define IPD_BIST_STATUS_63_29 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
390
#define IPD_BIST_STATUS_PWQ_WQED UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
391
#define IPD_BIST_STATUS_PWQ_WP1 UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
392
#define IPD_BIST_STATUS_PWQ_POW UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
393
#define IPD_BIST_STATUS_IPQ_PBE1 UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
394
#define IPD_BIST_STATUS_IPQ_PBE0 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
395
#define IPD_BIST_STATUS_PBM3 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
396
#define IPD_BIST_STATUS_PBM2 UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
397
#define IPD_BIST_STATUS_PBM1 UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
398
#define IPD_BIST_STATUS_PBM0 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
399
#define IPD_BIST_STATUS_PBM_WORD UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
400
#define IPD_BIST_STATUS_PWQ1 UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
401
#define IPD_BIST_STATUS_PWQ0 UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
402
#define IPD_BIST_STATUS_PRC_OFF UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
403
#define IPD_BIST_STATUS_IPD_OLD UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
404
#define IPD_BIST_STATUS_IPD_NEW UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_ipdreg.h
405
#define IPD_BIST_STATUS_PWP UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_mpireg.h
49
#define MPI_CFG_XXX_63_29 UINT64_C(0xffffffffe0000000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
50
#define MPI_CFG_CLKDIV UINT64_C(0x000000001fff0000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
51
#define MPI_CFG_XXX_15_12 UINT64_C(0x000000000000f000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
52
#define MPI_CFG_CSLATE UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_mpireg.h
53
#define MPI_CFG_TRITX UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_mpireg.h
54
#define MPI_CFG_IDLECLKS UINT64_C(0x0000000000000300)
sys/arch/mips/cavium/dev/octeon_mpireg.h
55
#define MPI_CFG_CSHI UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_mpireg.h
56
#define MPI_CFG_CSENA UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_mpireg.h
57
#define MPI_CFG_INT_ENA UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_mpireg.h
58
#define MPI_CFG_LSBFIRST UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_mpireg.h
59
#define MPI_CFG_WIREOR UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_mpireg.h
60
#define MPI_CFG_CLK_CONT UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_mpireg.h
61
#define MPI_CFG_IDLELO UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_mpireg.h
62
#define MPI_CFG_ENABLE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_mpireg.h
64
#define MPI_STS_XXX_63_13 UINT64_C(0xffffffffffffe000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
65
#define MPI_STS_RXNUM UINT64_C(0x0000000000001f00)
sys/arch/mips/cavium/dev/octeon_mpireg.h
66
#define MPI_STS_XXX_7_1 UINT64_C(0x00000000000000fe)
sys/arch/mips/cavium/dev/octeon_mpireg.h
67
#define MPI_STS_BUSY UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_mpireg.h
69
#define MPI_TX_XXX_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
70
#define MPI_TX_LEAVECS UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
71
#define MPI_TX_XXX_15_13 UINT64_C(0x000000000000e000)
sys/arch/mips/cavium/dev/octeon_mpireg.h
72
#define MPI_TX_TXNUM UINT64_C(0x0000000000001f00)
sys/arch/mips/cavium/dev/octeon_mpireg.h
73
#define MPI_TX_XXX_7_5 UINT64_C(0x00000000000000e0)
sys/arch/mips/cavium/dev/octeon_mpireg.h
74
#define MPI_TX_TOTNUM UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_mpireg.h
76
#define MPI_DATX_XXX_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_mpireg.h
77
#define MPI_DATX_DATA UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_npireg.h
101
#define NPI_DBG_SELECT_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
102
#define NPI_DBG_SELECT_DBG_SEL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
104
#define NPI_CTL_STATUS_XXX_63 UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
105
#define NPI_DBG_SELECT_DBG_SEL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
107
#define NPI_CTL_STATUS_XXX_63 UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
108
#define NPI_CTL_STATUS_CHIP_REV UINT64_C(0x7f80000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
109
#define NPI_CTL_STATUS_DIS_PNIW UINT64_C(0x0040000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
110
#define NPI_CTL_STATUS_SPR5 UINT64_C(0x0020000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
111
#define NPI_CTL_STATUS_SPR4 UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
112
#define NPI_CTL_STATUS_SPR8 UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
113
#define NPI_CTL_STATUS_OUT0_ENB UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
114
#define NPI_CTL_STATUS_SPR3 UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
115
#define NPI_CTL_STATUS_SPR2 UINT64_C(0x0001000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
116
#define NPI_CTL_STATUS_SPR7 UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
117
#define NPI_CTL_STATUS_INS0_ENB UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
118
#define NPI_CTL_STATUS_SPR1 UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
119
#define NPI_CTL_STATUS_SPR0 UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
120
#define NPI_CTL_STATUS_SPR6 UINT64_C(0x0000080000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
121
#define NPI_CTL_STATUS_INS0_64B UINT64_C(0x0000040000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
122
#define NPI_CTL_STATUS_PCI_WDIS UINT64_C(0x0000020000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
123
#define NPI_CTL_STATUS_WAIT_COM UINT64_C(0x0000010000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
124
#define NPI_CTL_STATUS_SPARES1 UINT64_C(0x000000e000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
125
#define NPI_CTL_STATUS_MAX_WORD UINT64_C(0x0000001f00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
126
#define NPI_CTL_STATUS_SPARES0 UINT64_C(0x00000000fffffc00)
sys/arch/mips/cavium/dev/octeon_npireg.h
127
#define NPI_CTL_STATUS_TIMER UINT64_C(0x00000000000003ff)
sys/arch/mips/cavium/dev/octeon_npireg.h
129
#define NPI_INT_SUM_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
130
#define NPI_INT_SUM_Q1_A_F UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
131
#define NPI_INT_SUM_Q1_S_E UINT64_C(0x1000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
132
#define NPI_INT_SUM_PDF_P_F UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
133
#define NPI_INT_SUM_PDF_P_E UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
134
#define NPI_INT_SUM_PCF_P_F UINT64_C(0x0200000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
135
#define NPI_INT_SUM_PCF_P_E UINT64_C(0x0100000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
136
#define NPI_INT_SUM_RDX_S_E UINT64_C(0x0080000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
137
#define NPI_INT_SUM_RWX_S_E UINT64_C(0x0040000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
138
#define NPI_INT_SUM_PNC_A_F UINT64_C(0x0020000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
139
#define NPI_INT_SUM_PNC_S_F UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
140
#define NPI_INT_SUM_COM_A_F UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
141
#define NPI_INT_SUM_COM_S_E UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
142
#define NPI_INT_SUM_Q3_A_F UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
143
#define NPI_INT_SUM_Q3_S_E UINT64_C(0x0001000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
144
#define NPI_INT_SUM_Q2_A_F UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
145
#define NPI_INT_SUM_Q2_S_E UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
146
#define NPI_INT_SUM_PCR_A_F UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
147
#define NPI_INT_SUM_PCR_S_E UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
148
#define NPI_INT_SUM_FCR_A_F UINT64_C(0x0000080000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
149
#define NPI_INT_SUM_FCR_S_E UINT64_C(0x0000040000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
150
#define NPI_INT_SUM_IOBDMA UINT64_C(0x0000020000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
151
#define NPI_INT_SUM_P_DPERR UINT64_C(0x0000010000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
152
#define NPI_INT_SUM_WIN_RTO UINT64_C(0x0000008000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
153
#define NPI_INT_SUM_SPR17 UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
154
#define NPI_INT_SUM_SPR16 UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
155
#define NPI_INT_SUM_SPR26 UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
156
#define NPI_INT_SUM_IO_PPERR UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
157
#define NPI_INT_SUM_SPR15 UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
158
#define NPI_INT_SUM_SPR14 UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
159
#define NPI_INT_SUM_SPR25 UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
160
#define NPI_INT_SUM_P0_PTOUT UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
161
#define NPI_INT_SUM_SPR13 UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
162
#define NPI_INT_SUM_SPR12 UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
163
#define NPI_INT_SUM_SPR24 UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
164
#define NPI_INT_SUM_P0_PPERR UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
165
#define NPI_INT_SUM_SPR11 UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
166
#define NPI_INT_SUM_SPR10 UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
167
#define NPI_INT_SUM_SPR23 UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
168
#define NPI_INT_SUM_G0_RTOUT UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_npireg.h
169
#define NPI_INT_SUM_SPR9 UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_npireg.h
170
#define NPI_INT_SUM_SPR8 UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_npireg.h
171
#define NPI_INT_SUM_SPR22 UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_npireg.h
172
#define NPI_INT_SUM_P0_PERR UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_npireg.h
173
#define NPI_INT_SUM_SPR7 UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_npireg.h
174
#define NPI_INT_SUM_SPR6 UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_npireg.h
175
#define NPI_INT_SUM_SPR21 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
176
#define NPI_INT_SUM_P0_RTOUT UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_npireg.h
177
#define NPI_INT_SUM_SPR5 UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_npireg.h
178
#define NPI_INT_SUM_SPR4 UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_npireg.h
179
#define NPI_INT_SUM_SPR20 UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_npireg.h
180
#define NPI_INT_SUM_IO_OVERF UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_npireg.h
181
#define NPI_INT_SUM_SPR3 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_npireg.h
182
#define NPI_INT_SUM_SPR2 UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_npireg.h
183
#define NPI_INT_SUM_SPR19 UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_npireg.h
184
#define NPI_INT_SUM_IO_RTOUT UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_npireg.h
185
#define NPI_INT_SUM_SPR1 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_npireg.h
186
#define NPI_INT_SUM_SPR0 UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_npireg.h
187
#define NPI_INT_SUM_SPR18 UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
188
#define NPI_INT_SUM_PO0_2SML UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
189
#define NPI_INT_SUM_PCI_RSL UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_npireg.h
190
#define NPI_INT_SUM_RML_TWO UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_npireg.h
191
#define NPI_INT_SUM_RML_RTO UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_npireg.h
193
#define NPI_INT_ENB_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
194
#define NPI_INT_ENB_Q1_A_F UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
195
#define NPI_INT_ENB_Q1_S_E UINT64_C(0x1000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
196
#define NPI_INT_ENB_PDF_P_F UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
197
#define NPI_INT_ENB_PDF_P_E UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
198
#define NPI_INT_ENB_PCF_P_F UINT64_C(0x0200000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
199
#define NPI_INT_ENB_PCF_P_E UINT64_C(0x0100000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
200
#define NPI_INT_ENB_RDX_S_E UINT64_C(0x0080000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
201
#define NPI_INT_ENB_RWX_S_E UINT64_C(0x0040000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
202
#define NPI_INT_ENB_PNC_A_F UINT64_C(0x0020000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
203
#define NPI_INT_ENB_PNC_S_F UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
204
#define NPI_INT_ENB_COM_A_F UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
205
#define NPI_INT_ENB_COM_S_E UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
206
#define NPI_INT_ENB_Q3_A_F UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
207
#define NPI_INT_ENB_Q3_S_E UINT64_C(0x0001000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
208
#define NPI_INT_ENB_Q2_A_F UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
209
#define NPI_INT_ENB_Q2_S_E UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
210
#define NPI_INT_ENB_PCR_A_F UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
211
#define NPI_INT_ENB_PCR_S_E UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
212
#define NPI_INT_ENB_FCR_A_F UINT64_C(0x0000080000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
213
#define NPI_INT_ENB_FCR_S_E UINT64_C(0x0000040000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
214
#define NPI_INT_ENB_IOBDMA UINT64_C(0x0000020000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
215
#define NPI_INT_ENB_P_DPERR UINT64_C(0x0000010000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
216
#define NPI_INT_ENB_WIN_RTO UINT64_C(0x0000008000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
217
#define NPI_INT_ENB_SPR17 UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
218
#define NPI_INT_ENB_SPR16 UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
219
#define NPI_INT_ENB_SPR26 UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
220
#define NPI_INT_ENB_IO_PPERR UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
221
#define NPI_INT_ENB_SPR15 UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
222
#define NPI_INT_ENB_SPR14 UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
223
#define NPI_INT_ENB_SPR25 UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
224
#define NPI_INT_ENB_P0_PTOUT UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
225
#define NPI_INT_ENB_SPR13 UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
226
#define NPI_INT_ENB_SPR12 UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
227
#define NPI_INT_ENB_SPR24 UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
228
#define NPI_INT_ENB_P0_PPERR UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
229
#define NPI_INT_ENB_SPR11 UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
230
#define NPI_INT_ENB_SPR10 UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
231
#define NPI_INT_ENB_SPR23 UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
232
#define NPI_INT_ENB_G0_RTOUT UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_npireg.h
233
#define NPI_INT_ENB_SPR9 UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_npireg.h
234
#define NPI_INT_ENB_SPR8 UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_npireg.h
235
#define NPI_INT_ENB_SPR22 UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_npireg.h
236
#define NPI_INT_ENB_P0_PERR UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_npireg.h
237
#define NPI_INT_ENB_SPR7 UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_npireg.h
238
#define NPI_INT_ENB_SPR6 UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_npireg.h
239
#define NPI_INT_ENB_SPR21 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
240
#define NPI_INT_ENB_P0_RTOUT UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_npireg.h
241
#define NPI_INT_ENB_SPR5 UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_npireg.h
242
#define NPI_INT_ENB_SPR4 UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_npireg.h
243
#define NPI_INT_ENB_SPR20 UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_npireg.h
244
#define NPI_INT_ENB_IO_OVERF UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_npireg.h
245
#define NPI_INT_ENB_SPR3 UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_npireg.h
246
#define NPI_INT_ENB_SPR2 UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_npireg.h
247
#define NPI_INT_ENB_SPR19 UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_npireg.h
248
#define NPI_INT_ENB_IO_RTOUT UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_npireg.h
249
#define NPI_INT_ENB_SPR1 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_npireg.h
250
#define NPI_INT_ENB_SPR0 UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_npireg.h
251
#define NPI_INT_ENB_SPR18 UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
252
#define NPI_INT_ENB_PO0_2SML UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
253
#define NPI_INT_ENB_PCI_RSL UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_npireg.h
254
#define NPI_INT_ENB_RML_TWO UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_npireg.h
255
#define NPI_INT_ENB_RML_RTO UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_npireg.h
257
#define NPI_MEM_ACCESS_SUBIDX_XXX_63_38 UINT64_C(0xffffffc000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
258
#define NPI_MEM_ACCESS_SUBIDX_SHORT UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
259
#define NPI_MEM_ACCESS_SUBIDX_NMERGE UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
260
#define NPI_MEM_ACCESS_SUBIDX_ESR UINT64_C(0x0000000c00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
261
#define NPI_MEM_ACCESS_SUBIDX_ESW UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
262
#define NPI_MEM_ACCESS_SUBIDX_NSR UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
263
#define NPI_MEM_ACCESS_SUBIDX_NSW UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
264
#define NPI_MEM_ACCESS_SUBIDX_ROR UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
265
#define NPI_MEM_ACCESS_SUBIDX_ROW UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
266
#define NPI_MEM_ACCESS_SUBIDX_BA UINT64_C(0x000000000fffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
268
#define NPI_PCI_READ_CMD_XXX_63_11 UINT64_C(0xfffffffffffff800)
sys/arch/mips/cavium/dev/octeon_npireg.h
269
#define NPI_PCI_READ_CMD_CMD_SIZE UINT64_C(0x00000000000007ff)
sys/arch/mips/cavium/dev/octeon_npireg.h
271
#define NPI_NUM_DESC_OUTPUT0_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
272
#define NPI_NUM_DESC_OUTPUT0_SIZE UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
274
#define NPI_BASE_ADDR_INPUT0_BADDR UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_npireg.h
275
#define NPI_BASE_ADDR_INPUT0_XXX_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_npireg.h
277
#define NPI_SIZE_INPUT0_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
278
#define NPI_SIZE_INPUT0_SIZE UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
280
#define PCI_READ_TIMEOUT_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
281
#define PCI_READ_TIMEOUT_ENB UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
282
#define PCI_READ_TIMEOUT_CNT UINT64_C(0x000000007fffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
284
#define NPI_BASE_ADDR_OUTPUT0_BADDR UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_npireg.h
285
#define NPI_BASE_ADDR_OUTPUT0_XXX_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_npireg.h
287
#define NPI_PCI_BURST_SIZE_XXX_63_14 UINT64_C(0xffffffffffffc000)
sys/arch/mips/cavium/dev/octeon_npireg.h
288
#define NPI_PCI_BURST_SIZE_WR_BRST UINT64_C(0x0000000000003f80)
sys/arch/mips/cavium/dev/octeon_npireg.h
289
#define NPI_PCI_BURST_SIZE_RD_BRST UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_npireg.h
291
#define NPI_BUFF_SIZE_OUTPUT0_XXX_63_23 UINT64_C(0xffffffffff800000)
sys/arch/mips/cavium/dev/octeon_npireg.h
292
#define NPI_BUFF_SIZE_OUTPUT0_ISIZE UINT64_C(0x00000000007f0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
293
#define NPI_BUFF_SIZE_OUTPUT0_BSIZE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
295
#define NPI_OUTPUT_CONTROL_XXX_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
296
#define NPI_OUTPUT_CONTROL_SPR5 UINT64_C(0x0000e00000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
297
#define NPI_OUTPUT_CONTROL_P0_BMODE UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
298
#define NPI_OUTPUT_CONTROL_SPR4 UINT64_C(0x00000fff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
299
#define NPI_OUTPUT_CONTROL_O0_ES UINT64_C(0x00000000c0000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
300
#define NPI_OUTPUT_CONTROL_O0_NS UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
301
#define NPI_OUTPUT_CONTROL_O0_RO UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
302
#define NPI_OUTPUT_CONTROL_SPR3 UINT64_C(0x000000000e000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
303
#define NPI_OUTPUT_CONTROL_O0_CSRM UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
304
#define NPI_OUTPUT_CONTROL_SPR2 UINT64_C(0x0000000000f00000)
sys/arch/mips/cavium/dev/octeon_npireg.h
305
#define NPI_OUTPUT_CONTROL_SPR1 UINT64_C(0x00000000000e0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
306
#define NPI_OUTPUT_CONTROL_IPTR_O0 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
307
#define NPI_OUTPUT_CONTROL_SPR0 UINT64_C(0x000000000000fff0)
sys/arch/mips/cavium/dev/octeon_npireg.h
308
#define NPI_OUTPUT_CONTROL_ESR_SL0 UINT64_C(0x000000000000000c)
sys/arch/mips/cavium/dev/octeon_npireg.h
309
#define NPI_OUTPUT_CONTROL_NSR_SL0 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_npireg.h
310
#define NPI_OUTPUT_CONTROL_ROR_SL0 UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_npireg.h
312
#define NPI_LOWP_IBUFF_SADDR_XXX_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
313
#define NPI_LOWP_IBUFF_SADDR_SADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
315
#define NPI_HIGHP_IBUFF_SADDR_XXX_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
316
#define NPI_HIGHP_IBUFF_SADDR_SADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
318
#define NPI_LOWP_DBELL_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
319
#define NPI_LOWP_DBELL_DBELL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
321
#define NPI_HIGHP_DBELL_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
322
#define NPI_HIGHP_DBELL_DBELL UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
324
#define NPI_DMA_CONTROL_XXX_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
325
#define NPI_DMA_CONTROL_B0_LEND UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
326
#define NPI_DMA_CONTROL_DWB_DENB UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
327
#define NPI_DMA_CONTROL_DWB_ICHK UINT64_C(0x00000003fe000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
328
#define NPI_DMA_CONTROL_FPA_QUE UINT64_C(0x0000000001c00000)
sys/arch/mips/cavium/dev/octeon_npireg.h
329
#define NPI_DMA_CONTROL_O_ADD1 UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_npireg.h
330
#define NPI_DMA_CONTROL_O_RO UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_npireg.h
331
#define NPI_DMA_CONTROL_O_NS UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_npireg.h
332
#define NPI_DMA_CONTROL_O_ES UINT64_C(0x0000000000060000)
sys/arch/mips/cavium/dev/octeon_npireg.h
333
#define NPI_DMA_CONTROL_O_MODE UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
334
#define NPI_DMA_CONTROL_HP_ENB UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_npireg.h
335
#define NPI_DMA_CONTROL_LP_ENB UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_npireg.h
336
#define NPI_DMA_CONTROL_CSIZE UINT64_C(0x0000000000003fff)
sys/arch/mips/cavium/dev/octeon_npireg.h
338
#define NPI_PCI_INT_ARB_CFG_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_npireg.h
339
#define NPI_PCI_INT_ARB_CFG_EN UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
340
#define NPI_PCI_INT_ARB_CFG_PARK_MOD UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
341
#define NPI_PCI_INT_ARB_CFG_PARK_DEV UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_npireg.h
343
#define NPI_INPUT_CONTROL_XXX_63_22 UINT64_C(0xffffffffffc00000)
sys/arch/mips/cavium/dev/octeon_npireg.h
344
#define NPI_INPUT_CONTROL_PBP_DHI UINT64_C(0x00000000003ffe00)
sys/arch/mips/cavium/dev/octeon_npireg.h
345
#define NPI_INPUT_CONTROL_D_NSR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_npireg.h
346
#define NPI_INPUT_CONTROL_D_ESR UINT64_C(0x00000000000000c0)
sys/arch/mips/cavium/dev/octeon_npireg.h
347
#define NPI_INPUT_CONTROL_D_ROR UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_npireg.h
348
#define NPI_INPUT_CONTROL_USE_CSR UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
349
#define NPI_INPUT_CONTROL_NSR UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
350
#define NPI_INPUT_CONTROL_ESR UINT64_C(0x0000000000000006)
sys/arch/mips/cavium/dev/octeon_npireg.h
351
#define NPI_INPUT_CONTROL_ROR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_npireg.h
353
#define NPI_DMA_LOWP_COUNTS_XXX_63_39 UINT64_C(0xffffff8000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
354
#define NPI_DMA_LOWP_COUNTS_FCNT UINT64_C(0x0000007f00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
355
#define NPI_DMA_LOWP_COUNTS_DBELL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
357
#define NPI_DMA_HIGHP_COUNTS_XXX_63_39 UINT64_C(0xffffff8000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
358
#define NPI_DMA_HIGHP_COUNTS_FCNT UINT64_C(0x0000007f00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
359
#define NPI_DMA_HIGHP_COUNTS_DBELL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
361
#define NPI_DMA_LOWP_NADDR_XXX_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
362
#define NPI_DMA_LOWP_NADDR_STATE UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
363
#define NPI_DMA_LOWP_NADDR_ADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
365
#define NPI_DMA_HIGHP_NADDR_XXX_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
366
#define NPI_DMA_HIGHP_NADDR_STATE UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
367
#define NPI_DMA_HIGHP_NADDR_ADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
369
#define NPI_P0_PAIR_CNTS_XXX_63_37 UINT64_C(0xffffffe000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
370
#define NPI_P0_PAIR_CNTS_FCNT UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
371
#define NPI_P0_PAIR_CNTS_AVAIL UINT64_C(0x00000000c0000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
373
#define NPI_P0_DBPAIR_ADDR_XXX_63 UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
374
#define NPI_P0_DBPAIR_ADDR_STATE UINT64_C(0x6000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
375
#define NPI_P0_DBPAIR_ADDR_NADDR UINT64_C(0x1fffffffffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
377
#define NPI_P0_INSTR_CNTS_XXX_63_38 UINT64_C(0xffffffc000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
378
#define NPI_P0_INSTR_CNTS_FCNT UINT64_C(0x0000003f00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
379
#define NPI_P0_INSTR_CNTS_AVAIL UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
381
#define NPI_P0_INSTR_ADDR_STATE UINT64_C(0xe000000000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
382
#define NPI_P0_INSTR_ADDR_NADDR UINT64_C(0x1fffffffffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
384
#define NPI_WIN_READ_TO_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
385
#define NPI_WIN_READ_TO_TIME UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
387
#define DBG_DATA_XXX_63_31 UINT64_C(0xffffffff80000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
388
#define DBG_DATA_PLL_MUL UINT64_C(0x0000000070000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
389
#define DBG_DATA_XXX_27_23 UINT64_C(0x000000000f800000)
sys/arch/mips/cavium/dev/octeon_npireg.h
390
#define DBG_DATA_C_MUL UINT64_C(0x00000000007c0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
391
#define DBG_DATA_DSEL_EXT UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_npireg.h
392
#define DBG_DATA_DATA UINT64_C(0x000000000001ffff)
sys/arch/mips/cavium/dev/octeon_npireg.h
394
#define NPI_PORT_BP_CONTROL_XXX_63_5 UINT64_C(0xffffffffffffffe0)
sys/arch/mips/cavium/dev/octeon_npireg.h
395
#define NPI_PORT_BP_CONTROL_BP_ON UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
396
#define NPI_PORT_BP_CONTROL_ENB UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_npireg.h
398
#define NPI_PORT32_INSTR_HDR_XXX_63_44 UINT64_C(0xfffff00000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
399
#define NPI_PORT32_INSTR_HDR_PBP UINT64_C(0x0000080000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
400
#define NPI_PORT32_INSTR_HDR_XXX_42_38 UINT64_C(0x000007c000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
401
#define NPI_PORT32_INSTR_HDR_RPARMODE UINT64_C(0x0000003000000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
402
#define NPI_PORT32_INSTR_HDR_XXX_35 UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
403
#define NPI_PORT32_INSTR_HDR_RSKP_LEN UINT64_C(0x00000007f0000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
404
#define NPI_PORT32_INSTR_HDR_XXX_27_22 UINT64_C(0x000000000fc00000)
sys/arch/mips/cavium/dev/octeon_npireg.h
405
#define NPI_PORT32_INSTR_HDR_USE_IHDR UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_npireg.h
406
#define NPI_PORT32_INSTR_HDR_XXX_20_16 UINT64_C(0x00000000001f0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
407
#define NPI_PORT32_INSTR_HDR_PAR_MODE UINT64_C(0x000000000000c000)
sys/arch/mips/cavium/dev/octeon_npireg.h
408
#define NPI_PORT32_INSTR_HDR_XXX_13 UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_npireg.h
409
#define NPI_PORT32_INSTR_HDR_SKP_LEN UINT64_C(0x0000000000001fc0)
sys/arch/mips/cavium/dev/octeon_npireg.h
410
#define NPI_PORT32_INSTR_HDR_XXX_5_0 UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_npireg.h
412
#define NPI_BIST_STATUS_XXX_63_20 UINT64_C(0xfffffffffff00000)
sys/arch/mips/cavium/dev/octeon_npireg.h
413
#define NPI_BIST_STATUS_CSR_BS UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_npireg.h
414
#define NPI_BIST_STATUS_DIF_BS UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_npireg.h
415
#define NPI_BIST_STATUS_RDP_BS UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_npireg.h
416
#define NPI_BIST_STATUS_PCNC_BS UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
417
#define NPI_BIST_STATUS_PCN_BS UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_npireg.h
418
#define NPI_BIST_STATUS_RDN_BS UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_npireg.h
419
#define NPI_BIST_STATUS_PCAC_BS UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_npireg.h
420
#define NPI_BIST_STATUS_PCAD_BS UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_npireg.h
421
#define NPI_BIST_STATUS_RDNL_BS UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_npireg.h
422
#define NPI_BIST_STATUS_PGF_BS UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_npireg.h
423
#define NPI_BIST_STATUS_PIG_BS UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_npireg.h
424
#define NPI_BIST_STATUS_POF0_BS UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_npireg.h
425
#define NPI_BIST_STATUS_POF1_BS UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_npireg.h
426
#define NPI_BIST_STATUS_POF2_BS UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_npireg.h
427
#define NPI_BIST_STATUS_POF3_BS UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_npireg.h
428
#define NPI_BIST_STATUS_POS_BS UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
429
#define NPI_BIST_STATUS_NUS_BS UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
430
#define NPI_BIST_STATUS_DOB_BS UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_npireg.h
431
#define NPI_BIST_STATUS_PDF_BS UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_npireg.h
432
#define NPI_BIST_STATUS_DPI_BS UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_npireg.h
79
#define NPI_RSL_INT_BLOCKS_XXX_63_31 UINT64_C(0xffffffff80000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
80
#define NPI_RSL_INT_BLOCKS_IOB UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_npireg.h
81
#define NPI_RSL_INT_BLOCKS_XXX_29_23 UINT64_C(0x000000003f800000)
sys/arch/mips/cavium/dev/octeon_npireg.h
82
#define NPI_RSL_INT_BLOCKS_ASX0 UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_npireg.h
83
#define NPI_RSL_INT_BLOCKS_XXX_21 UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_npireg.h
84
#define NPI_RSL_INT_BLOCKS_PIP UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_npireg.h
85
#define NPI_RSL_INT_BLOCKS_XXX_19_18 UINT64_C(0x00000000000c0000)
sys/arch/mips/cavium/dev/octeon_npireg.h
86
#define NPI_RSL_INT_BLOCKS_LMC UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_npireg.h
87
#define NPI_RSL_INT_BLOCKS_L2C UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_npireg.h
88
#define NPI_RSL_INT_BLOCKS_XXX_15_13 UINT64_C(0x000000000000e000)
sys/arch/mips/cavium/dev/octeon_npireg.h
89
#define NPI_RSL_INT_BLOCKS_POW UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_npireg.h
90
#define NPI_RSL_INT_BLOCKS_TIM UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_npireg.h
91
#define NPI_RSL_INT_BLOCKS_PKO UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_npireg.h
92
#define NPI_RSL_INT_BLOCKS_IPD UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_npireg.h
93
#define NPI_RSL_INT_BLOCKS_XXX_8_6 UINT64_C(0x00000000000001c0)
sys/arch/mips/cavium/dev/octeon_npireg.h
94
#define NPI_RSL_INT_BLOCKS_FPA UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_npireg.h
95
#define NPI_RSL_INT_BLOCKS_XXX_4 UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_npireg.h
96
#define NPI_RSL_INT_BLOCKS_NPI UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_npireg.h
97
#define NPI_RSL_INT_BLOCKS_GMX1 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_npireg.h
98
#define NPI_RSL_INT_BLOCKS_GMX0 UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_npireg.h
99
#define NPI_RSL_INT_BLOCKS_MIO UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pipreg.h
213
#define PIP_BIST_STATUS_63_13 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
214
#define PIP_BIST_STATUS_BIST UINT64_C(0x000000000003ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
219
#define PIP_INT_REG_63_9 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_pipreg.h
220
#define PIP_INT_REG_BEPERR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_pipreg.h
221
#define PIP_INT_REG_FEPERR UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_pipreg.h
222
#define PIP_INT_REG_6 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_pipreg.h
223
#define PIP_INT_REG_SKPRUNT UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_pipreg.h
224
#define PIP_INT_REG_BADTAG UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_pipreg.h
225
#define PIP_INT_REG_PRTNXA UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pipreg.h
232
#define PIP_INT_EN_63_9 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_pipreg.h
233
#define PIP_INT_EN_BEPERR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_pipreg.h
234
#define PIP_INT_EN_FEPERR UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_pipreg.h
235
#define PIP_INT_EN_6 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_pipreg.h
236
#define PIP_INT_EN_SKPRUNT UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_pipreg.h
237
#define PIP_INT_EN_BADTAG UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_pipreg.h
238
#define PIP_INT_EN_PRTNXA UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pipreg.h
245
#define PIP_STAT_CTL_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_pipreg.h
246
#define PIP_STAT_CTL_RDCLR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pipreg.h
251
#define PIP_GBL_CTL_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
252
#define PIP_GBL_CTL_IGNRS UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
253
#define PIP_GBL_CTL_VS_WQE UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
254
#define PIP_GBL_CTL_VS_QOS UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
255
#define PIP_GBL_CTL_L2MAL UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
256
#define PIP_GBL_CTL_TCP_FLAG UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
257
#define PIP_GBL_CTL_L4_LEN UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_pipreg.h
258
#define PIP_GBL_CTL_L4_CHK UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_pipreg.h
259
#define PIP_GBL_CTL_L4_PRT UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_pipreg.h
260
#define PIP_GBL_CTL_L4_MAL UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_pipreg.h
261
#define PIP_GBL_CTL_7_6 UINT64_C(0x00000000000000c0)
sys/arch/mips/cavium/dev/octeon_pipreg.h
262
#define PIP_GBL_CTL_IP6_EEXT UINT64_C(0x0000000000000030)
sys/arch/mips/cavium/dev/octeon_pipreg.h
263
#define PIP_GBL_CTL_IP4_OPTS UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pipreg.h
264
#define PIP_GBL_CTL_IP_HOP UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_pipreg.h
265
#define PIP_GBL_CTL_IP_MAL UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_pipreg.h
266
#define PIP_GBL_CTL_IP_CHK UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pipreg.h
272
#define PIP_GBL_CFG_63_19 UINT64_C(0xfffffffffff80000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
273
#define PIP_GBL_CFG_TAG_SYN UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
274
#define PIP_GBL_CFG_IP6_UDP UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
275
#define PIP_GBL_CFG_MAX_L2 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
276
#define PIP_GBL_CFG_15_11 UINT64_C(0x000000000000f800)
sys/arch/mips/cavium/dev/octeon_pipreg.h
277
#define PIP_GBL_CFG_RAW_SHF UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_pipreg.h
278
#define PIP_GBL_CFG_7_3 UINT64_C(0x00000000000000f8)
sys/arch/mips/cavium/dev/octeon_pipreg.h
279
#define PIP_GBL_CFG_NIP_SHF_MASK UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pipreg.h
284
#define PIP_SFT_RST_63_17 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_pipreg.h
285
#define PIP_SFT_RST_RST UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pipreg.h
290
#define PIP_IP_OFFSET_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_pipreg.h
292
#define PIP_IP_OFFSET_MASK_OFFSET UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pipreg.h
297
#define PIP_TAG_SECRET_63_3 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
298
#define PIP_TAG_SECRET_DST UINT64_C(0x00000000ffff0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
299
#define PIP_TAG_SECRET_SRC UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
304
#define PIP_TAG_MASK_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
305
#define PIP_TAG_MASK_MASK UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
310
#define PIP_DEC_IPSECN_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
311
#define PIP_DEC_IPSECN_TCP UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
312
#define PIP_DEC_IPSECN_UDP UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
313
#define PIP_DEC_IPSECN_DPRT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
318
#define PIP_RAW_WORD_63_56 UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
319
#define PIP_RAW_WORD_WORD UINT64_C(0x00ffffffffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
324
#define PIP_QOS_VLAN_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_pipreg.h
325
#define PIP_QOS_VLAN_QOS UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pipreg.h
330
#define PIP_QOS_WATCHN_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
331
#define PIP_QOS_WATCHN_MASK UINT64_C(0x0000ffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
332
#define PIP_QOS_WATCHN_31_28 UINT64_C(0x00000000f0000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
333
#define PIP_QOS_WATCHN_GRP UINT64_C(0x000000000f000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
334
#define PIP_QOS_WATCHN_23 UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
335
#define PIP_QOS_WATCHN_WATCHER UINT64_C(0x0000000000700000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
336
#define PIP_QOS_WATCHN_19_18 UINT64_C(0x00000000000c0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
337
#define PIP_QOS_WATCHN_TYPE UINT64_C(0x0000000000030000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
338
#define PIP_QOS_WATCHN_15_0 UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
343
#define PIP_PRT_CFGN_63_53 UINT64_C(0xffe0000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
344
#define PIP_PRT_CFGN_PAD_LEN UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
345
#define PIP_PRT_CFGN_VLAN_LEN UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
346
#define PIP_PRT_CFGN_LENERR_EN UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
347
#define PIP_PRT_CFGN_MAXERR_EN UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
348
#define PIP_PRT_CFGN_MINERR_EN UINT64_C(0x0001000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
349
#define PIP_PRT_CFGN_GRP_WAT_47 UINT64_C(0x0000f00000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
350
#define PIP_PRT_CFGN_QOS_WAT_47 UINT64_C(0x00000f0000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
351
#define PIP_PRT_CFGN_39_37 UINT64_C(0x000000e000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
352
#define PIP_PRT_CFGN_RAWDRP UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
353
#define PIP_PRT_CFGN_TAG_INC UINT64_C(0x0000000c00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
354
#define PIP_PRT_CFGN_DYN_RS UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
355
#define PIP_PRT_CFGN_INST_HDR UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
356
#define PIP_PRT_CFGN_GRP_WAT UINT64_C(0x00000000f0000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
357
#define PIP_PRT_CFGN_27 UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
358
#define PIP_PRT_CFGN_QOS UINT64_C(0x0000000007000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
359
#define PIP_PRT_CFGN_QOS_WAT UINT64_C(0x0000000000f00000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
360
#define PIP_PRT_CFGN_19 UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
361
#define PIP_PRT_CFGN_SPARE UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
362
#define PIP_PRT_CFGN_QOS_DIFF UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
363
#define PIP_PRT_CFGN_QOS_VLAN UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
364
#define PIP_PRT_CFGN_15_13 UINT64_C(0x000000000000e000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
365
#define PIP_PRT_CFGN_CRC_EN UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
366
#define PIP_PRT_CFGN_11_10 UINT64_C(0x0000000000000c00)
sys/arch/mips/cavium/dev/octeon_pipreg.h
367
#define PIP_PRT_CFGN_MODE UINT64_C(0x0000000000000300)
sys/arch/mips/cavium/dev/octeon_pipreg.h
372
#define PIP_PRT_CFGN_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_pipreg.h
373
#define PIP_PRT_CFGN_SKIP UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_pipreg.h
378
#define PIP_PRT_TAGN_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
379
#define PIP_PRT_TAGN_GRPTAGBASE UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
380
#define PIP_PRT_TAGN_GRPTAGMASK UINT64_C(0x0000000f00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
381
#define PIP_PRT_TAGN_GRPTAG UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
382
#define PIP_PRT_TAGN_SPARE UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
383
#define PIP_PRT_TAGN_TAG_MODE UINT64_C(0x0000000030000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
384
#define PIP_PRT_TAGN_INC_VS UINT64_C(0x000000000c000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
385
#define PIP_PRT_TAGN_INC_VLAN UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
386
#define PIP_PRT_TAGN_INC_PRT UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
387
#define PIP_PRT_TAGN_IP6_DPRT UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
388
#define PIP_PRT_TAGN_IP4_DPRT UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
389
#define PIP_PRT_TAGN_IP6_SPRT UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
390
#define PIP_PRT_TAGN_IP4_SPRT UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
391
#define PIP_PRT_TAGN_IP6_NXTH UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
392
#define PIP_PRT_TAGN_IP4_PCTL UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
393
#define PIP_PRT_TAGN_IP6_DST UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
394
#define PIP_PRT_TAGN_IP4_SRC UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
395
#define PIP_PRT_TAGN_IP6_SRC UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
396
#define PIP_PRT_TAGN_IP4_DST UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
397
#define PIP_PRT_TAGN_TCP6_TAG UINT64_C(0x0000000000003000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
402
#define PIP_PRT_TAGN_TCP4_TAG UINT64_C(0x0000000000000c00)
sys/arch/mips/cavium/dev/octeon_pipreg.h
407
#define PIP_PRT_TAGN_IP6_TAG UINT64_C(0x0000000000000300)
sys/arch/mips/cavium/dev/octeon_pipreg.h
412
#define PIP_PRT_TAGN_IP4_TAG UINT64_C(0x00000000000000c0)
sys/arch/mips/cavium/dev/octeon_pipreg.h
417
#define PIP_PRT_TAGN_NON_TAG UINT64_C(0x0000000000000030)
sys/arch/mips/cavium/dev/octeon_pipreg.h
422
#define PIP_PRT_TAGN_GRP UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_pipreg.h
427
#define PIP_QOS_DIFF_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_pipreg.h
428
#define PIP_QOS_DIFF_QOS UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pipreg.h
433
#define PIP_TAG_INCN_63_8 UINT64_C(0xffffffffffffff00)
sys/arch/mips/cavium/dev/octeon_pipreg.h
434
#define PIP_TAG_INCN_EN UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
439
#define PIP_STAT0_PRTN_DRP_PKTS UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
440
#define PIP_STAT0_PRTN_DRP_OCTS UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
445
#define PIP_STAT1_PRTN_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
446
#define PIP_STAT1_PRTN_OCTS UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
451
#define PIP_STAT2_PRTN_PKTS UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
452
#define PIP_STAT2_PRTN_RAW UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
457
#define PIP_STAT3_PRTN_BCST UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
458
#define PIP_STAT3_PRTN_MCST UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
463
#define PIP_STAT4_PRTN_H65TO127 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
464
#define PIP_STAT4_PRTN_H64 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
469
#define PIP_STAT5_PRTN_H256TO511 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
470
#define PIP_STAT5_PRTN_H128TO255 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
475
#define PIP_STAT6_PRTN_H1024TO1518 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
476
#define PIP_STAT6_PRTN_H512TO1023 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
481
#define PIP_STAT7_PRTN_FCS UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
482
#define PIP_STAT7_PRTN_H1519 UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
487
#define PIP_STAT8_PRTN_FRAG UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
488
#define PIP_STAT8_PRTN_UNDERSZ UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
493
#define PIP_STAT9_PRTN_JABBER UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
494
#define PIP_STAT9_PRTN_OVERSZ UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
499
#define PIP_STAT_INB_PKTSN UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
500
#define PIP_STAT_INB_PKTSN_PKTS UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
505
#define PIP_STAT_INB_OCTSN UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
506
#define PIP_STAT_INB_OCTSN_OCTS UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
511
#define PIP_STAT_INB_ERRSN UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
512
#define PIP_STAT_INB_ERRSN_OCTS UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
518
#define PIP_WQE_WORD0_HW_CSUM UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
519
#define PIP_WQE_WORD0_47_40 UINT64_C(0x0000ff0000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
520
#define PIP_WQE_WORD0_POW_NEXT_PTR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
523
#define PIP_WQE_WORD1_LEN UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
524
#define PIP_WQE_WORD1_IPRT UINT64_C(0x0000fc0000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
525
#define PIP_WQE_WORD1_QOS UINT64_C(0x0000038000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
526
#define PIP_WQE_WORD1_GRP UINT64_C(0x0000007800000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
527
#define PIP_WQE_WORD1_TT UINT64_C(0x0000000700000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
528
#define PIP_WQE_WORD1_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
531
#define PIP_WQE_WORD2_RAWFULL_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
532
#define PIP_WQE_WORD2_RAWFULL_PIP_RAW_WORD UINT64_C(0x00ffffffffffffff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
534
#define PIP_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
535
#define PIP_WQE_WORD2_IP_OFFSET UINT64_C(0x00ff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
536
#define PIP_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
537
#define PIP_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
538
#define PIP_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
539
#define PIP_WQE_WORD2_IP_VC UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
540
#define PIP_WQE_WORD2_IP_VLAN_ID UINT64_C(0x00000fff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
541
#define PIP_WQE_WORD2_IP_31_20 UINT64_C(0x00000000fff00000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
542
#define PIP_WQE_WORD2_IP_CO UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
543
#define PIP_WQE_WORD2_IP_TU UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
544
#define PIP_WQE_WORD2_IP_SE UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
545
#define PIP_WQE_WORD2_IP_V6 UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
546
#define PIP_WQE_WORD2_IP_15 UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
547
#define PIP_WQE_WORD2_IP_LE UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
548
#define PIP_WQE_WORD2_IP_FR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
549
#define PIP_WQE_WORD2_IP_IE UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
550
#define PIP_WQE_WORD2_IP_B UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_pipreg.h
551
#define PIP_WQE_WORD2_IP_M UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_pipreg.h
552
#define PIP_WQE_WORD2_IP_NI UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_pipreg.h
553
#define PIP_WQE_WORD2_IP_RE UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_pipreg.h
554
#define PIP_WQE_WORD2_IP_OPECODE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
556
#define PIP_WQE_WORD2_NOIP_BUFS UINT64_C(0xff00000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
557
#define PIP_WQE_WORD2_NOIP_55_48 UINT64_C(0x00ff000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
558
#define PIP_WQE_WORD2_NOIP_VV UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
559
#define PIP_WQE_WORD2_NOIP_VS UINT64_C(0x0000400000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
560
#define PIP_WQE_WORD2_NOIP_45 UINT64_C(0x0000200000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
561
#define PIP_WQE_WORD2_NOIP_VC UINT64_C(0x0000100000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
562
#define PIP_WQE_WORD2_NOIP_VLAN_ID UINT64_C(0x00000fff00000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
563
#define PIP_WQE_WORD2_NOIP_31_14 UINT64_C(0x00000000ffffc000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
564
#define PIP_WQE_WORD2_NOIP_IR UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
565
#define PIP_WQE_WORD2_NOIP_IA UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
566
#define PIP_WQE_WORD2_NOIP_B UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_pipreg.h
567
#define PIP_WQE_WORD2_NOIP_M UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_pipreg.h
568
#define PIP_WQE_WORD2_NOIP_NI UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_pipreg.h
569
#define PIP_WQE_WORD2_NOIP_RE UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_pipreg.h
570
#define PIP_WQE_WORD2_NOIP_OPECODE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_pipreg.h
573
#define PIP_WQE_WORD3_63 UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
574
#define PIP_WQE_WORD3_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
575
#define PIP_WQE_WORD3_58_56 UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
576
#define PIP_WQE_WORD3_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pipreg.h
577
#define PIP_WQE_WORD3_ADDR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
106
#define PKO_REG_FLAGS_63_7 UINT64_C(0xfffffffffffffff0)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
107
#define PKO_REG_FLAGS_RESET UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
108
#define PKO_REG_FLAGS_STORE_BE UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
109
#define PKO_REG_FLAGS_ENA_DWB UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
110
#define PKO_REG_FLAGS_ENA_PKO UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
115
#define PKO_REG_READ_IDX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
116
#define PKO_REG_READ_IDX_INC UINT64_C(0x000000000000ff00)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
117
#define PKO_REG_READ_IDX_IDX UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
122
#define PKO_REG_CMD_BUF_63_23 UINT64_C(0xffffffffff800000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
123
#define PKO_REG_CMD_BUF_POOL UINT64_C(0x0000000000700000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
124
#define PKO_REG_CMD_BUF_19_13 UINT64_C(0x00000000000fe000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
125
#define PKO_REG_CMD_BUF_SIZE UINT64_C(0x0000000000001fff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
130
#define PKO_REG_GMX_PORT_MODE_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
131
#define PKO_REG_GMX_PORT_MODE_MODE1 UINT64_C(0x0000000000000038)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
132
#define PKO_REG_GMX_PORT_MODE_MODE0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
137
#define PKO_REG_QUEUE_MODE_63_6 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
138
#define PKO_REG_QUEUE_MODE_MODE UINT64_C(0x000000000000000e)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
143
#define PKO_REG_BIST_RESULT_63_27 UINT64_C(0xfffffffff8000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
144
#define PKO_REG_BIST_RESULT_PSB2 UINT64_C(0x0000000007c00000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
145
#define PKO_REG_BIST_RESULT_COUNT UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
146
#define PKO_REG_BIST_RESULT_RIF UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
147
#define PKO_REG_BIST_RESULT_WIF UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
148
#define PKO_REG_BIST_RESULT_NCB UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
149
#define PKO_REG_BIST_RESULT_OUT UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
150
#define PKO_REG_BIST_RESULT_CRC UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
151
#define PKO_REG_BIST_RESULT_CHK UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
152
#define PKO_REG_BIST_RESULT_QSB UINT64_C(0x0000000000006000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
153
#define PKO_REG_BIST_RESULT_QCB UINT64_C(0x0000000000001800)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
154
#define PKO_REG_BIST_RESULT_PDB UINT64_C(0x0000000000000780)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
155
#define PKO_REG_BIST_RESULT_PSB UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
160
#define PKO_REG_ERROR_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
161
#define PKO_REG_ERROR_DOORBELL UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
162
#define PKO_REG_ERROR_PARITY UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
167
#define PKO_REG_INT_MASK_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
168
#define PKO_REG_INT_MASK_DOORBELL UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
169
#define PKO_REG_INT_MASK_PARITY UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
174
#define PKO_REG_DEBUG0_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
175
#define PKO_REG_DEBUG0_ASSERTS UINT64_C(0x000000000001ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
180
#define PKO_MEM_QUEUE_PTRS_S_TAIL UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
181
#define PKO_MEM_QUEUE_PTRS_STATIC_P UINT64_C(0x4000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
182
#define PKO_MEM_QUEUE_PTRS_STATIC_Q UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
183
#define PKO_MEM_QUEUE_PTRS_QOS_MASK UINT64_C(0x1fe0000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
184
#define PKO_MEM_QUEUE_PTRS_BUF_PTR UINT64_C(0x001ffffffffe0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
185
#define PKO_MEM_QUEUE_PTRS_TAIL UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
186
#define PKO_MEM_QUEUE_PTRS_IDX UINT64_C(0x000000000000e000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
187
#define PKO_MEM_QUEUE_PTRS_PID UINT64_C(0x0000000000001f80)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
188
#define PKO_MEM_QUEUE_PTRS_QID UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
193
#define PKO_MEM_QUEUE_QOS_63_61 UINT64_C(0xe000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
194
#define PKO_MEM_QUEUE_QOS_QOS_MASK UINT64_C(0x1fe0000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
195
#define PKO_MEM_QUEUE_QOS_52_13 UINT64_C(0x001fffffffffe000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
196
#define PKO_MEM_QUEUE_QOS_PID UINT64_C(0x0000000000001f80)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
197
#define PKO_MEM_QUEUE_QOS_QID UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
202
#define PKO_MEM_COUNT0_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
203
#define PKO_MEM_COUNT0_COUNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
208
#define PKO_MEM_COUNT1_63_48 UINT64_C(0xffff000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
209
#define PKO_MEM_COUNT1_COUNT UINT64_C(0x0000ffffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
214
#define PKO_MEM_DEBUG0_FAU UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
215
#define PKO_MEM_DEBUG0_CMD UINT64_C(0x0000000fffc00000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
216
#define PKO_MEM_DEBUG0_SEGS UINT64_C(0x00000000003f0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
217
#define PKO_MEM_DEBUG0_SIZE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
222
#define PKO_MEM_DEBUG1_I UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
223
#define PKO_MEM_DEBUG1_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
224
#define PKO_MEM_DEBUG1_POOL UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
225
#define PKO_MEM_DEBUG1_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
226
#define PKO_MEM_DEBUG1_PTR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
231
#define PKO_MEM_DEBUG2_I UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
232
#define PKO_MEM_DEBUG2_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
233
#define PKO_MEM_DEBUG2_POOL UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
234
#define PKO_MEM_DEBUG2_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
235
#define PKO_MEM_DEBUG2_PTR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
240
#define PKO_MEM_DEBUG3_I UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
241
#define PKO_MEM_DEBUG3_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
242
#define PKO_MEM_DEBUG3_POOL UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
243
#define PKO_MEM_DEBUG3_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
244
#define PKO_MEM_DEBUG3_PTR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
249
#define PKO_MEM_DEBUG4_DATA UINT64_C(0xffffffffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
254
#define PKO_MEM_DEBUG5_DWRI_MOD UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
255
#define PKO_MEM_DEBUG5_DWRI_SOP UINT64_C(0x4000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
256
#define PKO_MEM_DEBUG5_DWRI_LEN UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
257
#define PKO_MEM_DEBUG5_DWRI_CNT UINT64_C(0x1fff000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
258
#define PKO_MEM_DEBUG5_CMND_SIZ UINT64_C(0x0000ffff00000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
259
#define PKO_MEM_DEBUG5_UID UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
260
#define PKO_MEM_DEBUG5_XFER_WOR UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
261
#define PKO_MEM_DEBUG5_XFER_DWR UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
262
#define PKO_MEM_DEBUG5_CBUF_FRE UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
263
#define PKO_MEM_DEBUG5_27 UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
264
#define PKO_MEM_DEBUG5_CHK_MODE UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
265
#define PKO_MEM_DEBUG5_ACTIVE UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
266
#define PKO_MEM_DEBUG5_QOS UINT64_C(0x0000000001c00000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
267
#define PKO_MEM_DEBUG5_QCB_RIDX UINT64_C(0x00000000003e0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
268
#define PKO_MEM_DEBUG5_QID_OFF UINT64_C(0x000000000001c000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
269
#define PKO_MEM_DEBUG5_QID_BASE UINT64_C(0x0000000000003f80)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
270
#define PKO_MEM_DEBUG5_WAIT UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
271
#define PKO_MEM_DEBUG5_MINOR UINT64_C(0x0000000000000030)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
272
#define PKO_MEM_DEBUG5_MAJOR UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
277
#define PKO_MEM_DEBUG6_63_11 UINT64_C(0xfffffffffffff800)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
278
#define PKO_MEM_DEBUG6_QID_OFFM UINT64_C(0x0000000000000700)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
279
#define PKO_MEM_DEBUG6_STATIC_P UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
280
#define PKO_MEM_DEBUG6_WORK_MIN UINT64_C(0x0000000000000070)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
281
#define PKO_MEM_DEBUG6_DWRI_CHK UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
282
#define PKO_MEM_DEBUG6_DWRI_UID UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
283
#define PKO_MEM_DEBUG6_DWRI_MOD UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
288
#define PKO_MEM_DEBUG7_63_58 UINT64_C(0xfc00000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
289
#define PKO_MEM_DEBUG7_DWB UINT64_C(0x03fe000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
290
#define PKO_MEM_DEBUG7_START UINT64_C(0x0001ffffffff0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
291
#define PKO_MEM_DEBUG7_SIZE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
296
#define PKO_MEM_DEBUG8_QOS UINT64_C(0xf800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
297
#define PKO_MEM_DEBUG8_TAIL UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
298
#define PKO_MEM_DEBUG8_BUF_SIZ UINT64_C(0x03ffe00000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
299
#define PKO_MEM_DEBUG8_BUF_PTR UINT64_C(0x00001ffffffff000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
300
#define PKO_MEM_DEBUG8_QCB_WIDX UINT64_C(0x0000000000000fc0)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
301
#define PKO_MEM_DEBUG8_QCB_RIDX UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
306
#define PKO_MEM_DEBUG9_63_28 UINT64_C(0xfffffffff0000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
307
#define PKO_MEM_DEBUG9_DOORBELL UINT64_C(0x000000000fffff00)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
308
#define PKO_MEM_DEBUG9_7_5 UINT64_C(0x00000000000000e0)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
309
#define PKO_MEM_DEBUG9_S_TAIL UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
310
#define PKO_MEM_DEBUG9_STATIC_Q UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
311
#define PKO_MEM_DEBUG9_QOOS UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
316
#define PKO_MEM_DEBUG10_FAU UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
317
#define PKO_MEM_DEBUG10_CMD UINT64_C(0x0000000fffc00000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
318
#define PKO_MEM_DEBUG10_SEGS UINT64_C(0x00000000003f0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
319
#define PKO_MEM_DEBUG10_SIZE UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
324
#define PKO_MEM_DEBUG11_I UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
325
#define PKO_MEM_DEBUG11_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
326
#define PKO_MEM_DEBUG11_POOL UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
327
#define PKO_MEM_DEBUG11_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
328
#define PKO_MEM_DEBUG11_PTR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
333
#define PKO_MEM_DEBUG12_DATA UINT64_C(0xffffffffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
338
#define PKO_MEM_DEBUG13_63_51 UINT64_C(0xfff8000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
339
#define PKO_MEM_DEBUG13_WIDX UINT64_C(0x0007fffc00000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
340
#define PKO_MEM_DEBUG13_RIDX2 UINT64_C(0x00000003fffe0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
341
#define PKO_MEM_DEBUG13_WIDX2 UINT64_C(0x000000000001ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
346
#define PKO_MEM_DEBUG13_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
347
#define PKO_MEM_DEBUG13_RIDX UINT64_C(0x000000000001ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
352
#define PKO_CMD_WORD0_SZ1 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
353
#define PKO_CMD_WORD0_SZ0 UINT64_C(0x3000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
354
#define PKO_CMD_WORD0_S1 UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
355
#define PKO_CMD_WORD0_REG1 UINT64_C(0x07ff000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
356
#define PKO_CMD_WORD0_S0 UINT64_C(0x0000800000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
357
#define PKO_CMD_WORD0_REG0 UINT64_C(0x00007ff000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
358
#define PKO_CMD_WORD0_LE UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
359
#define PKO_CMD_WORD0_N2 UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
360
#define PKO_CMD_WORD0_Q UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
361
#define PKO_CMD_WORD0_R UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
362
#define PKO_CMD_WORD0_G UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
363
#define PKO_CMD_WORD0_IPOFFP1 UINT64_C(0x000000007f000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
364
#define PKO_CMD_WORD0_II UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
365
#define PKO_CMD_WORD0_DF UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
366
#define PKO_CMD_WORD0_SEGS UINT64_C(0x00000000003f0000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
367
#define PKO_CMD_WORD0_TOTALBYTES UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
372
#define PKO_CMD_WORD1_I UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
373
#define PKO_CMD_WORD1_BACK UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
374
#define PKO_CMD_WORD1_POOL UINT64_C(0x0700000000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
375
#define PKO_CMD_WORD1_SIZE UINT64_C(0x00ffff0000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
376
#define PKO_CMD_WORD1_ADDR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
381
#define PKO_CMD_WORD2_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
382
#define PKO_CMD_WORD2_PTR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
387
#define PKO_DOORBELL_WRITE_PID UINT64_C(0x000000000003f000)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
388
#define PKO_DOORBELL_WRITE_QID UINT64_C(0x0000000000000ff8)
sys/arch/mips/cavium/dev/octeon_pkoreg.h
390
#define PKO_DOORBELL_WRITE_WDC UINT64_C(0x00000000000fffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
100
#define POW_WS_PC8 UINT64_C(0x00016700000002c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
101
#define POW_WS_PC9 UINT64_C(0x00016700000002c8)
sys/arch/mips/cavium/dev/octeon_powreg.h
102
#define POW_WS_PC10 UINT64_C(0x00016700000002d0)
sys/arch/mips/cavium/dev/octeon_powreg.h
103
#define POW_WS_PC11 UINT64_C(0x00016700000002d8)
sys/arch/mips/cavium/dev/octeon_powreg.h
104
#define POW_WS_PC12 UINT64_C(0x00016700000002e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
105
#define POW_WS_PC13 UINT64_C(0x00016700000002e8)
sys/arch/mips/cavium/dev/octeon_powreg.h
106
#define POW_WS_PC14 UINT64_C(0x00016700000002f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
107
#define POW_WS_PC15 UINT64_C(0x00016700000002f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
108
#define POW_WA_PC0 UINT64_C(0x0001670000000300)
sys/arch/mips/cavium/dev/octeon_powreg.h
109
#define POW_WA_PC1 UINT64_C(0x0001670000000308)
sys/arch/mips/cavium/dev/octeon_powreg.h
110
#define POW_WA_PC2 UINT64_C(0x0001670000000310)
sys/arch/mips/cavium/dev/octeon_powreg.h
111
#define POW_WA_PC3 UINT64_C(0x0001670000000318)
sys/arch/mips/cavium/dev/octeon_powreg.h
112
#define POW_WA_PC4 UINT64_C(0x0001670000000320)
sys/arch/mips/cavium/dev/octeon_powreg.h
113
#define POW_WA_PC5 UINT64_C(0x0001670000000328)
sys/arch/mips/cavium/dev/octeon_powreg.h
114
#define POW_WA_PC6 UINT64_C(0x0001670000000330)
sys/arch/mips/cavium/dev/octeon_powreg.h
115
#define POW_WA_PC7 UINT64_C(0x0001670000000338)
sys/arch/mips/cavium/dev/octeon_powreg.h
116
#define POW_IQ_CNT0 UINT64_C(0x0001670000000340)
sys/arch/mips/cavium/dev/octeon_powreg.h
117
#define POW_IQ_CNT1 UINT64_C(0x0001670000000348)
sys/arch/mips/cavium/dev/octeon_powreg.h
118
#define POW_IQ_CNT2 UINT64_C(0x0001670000000350)
sys/arch/mips/cavium/dev/octeon_powreg.h
119
#define POW_IQ_CNT3 UINT64_C(0x0001670000000358)
sys/arch/mips/cavium/dev/octeon_powreg.h
120
#define POW_IQ_CNT4 UINT64_C(0x0001670000000360)
sys/arch/mips/cavium/dev/octeon_powreg.h
121
#define POW_IQ_CNT5 UINT64_C(0x0001670000000368)
sys/arch/mips/cavium/dev/octeon_powreg.h
122
#define POW_IQ_CNT6 UINT64_C(0x0001670000000370)
sys/arch/mips/cavium/dev/octeon_powreg.h
123
#define POW_IQ_CNT7 UINT64_C(0x0001670000000378)
sys/arch/mips/cavium/dev/octeon_powreg.h
124
#define POW_WA_COM_PC UINT64_C(0x0001670000000380)
sys/arch/mips/cavium/dev/octeon_powreg.h
125
#define POW_IQ_COM_CNT UINT64_C(0x0001670000000388)
sys/arch/mips/cavium/dev/octeon_powreg.h
126
#define POW_TS_PC UINT64_C(0x0001670000000390)
sys/arch/mips/cavium/dev/octeon_powreg.h
127
#define POW_DS_PC UINT64_C(0x0001670000000398)
sys/arch/mips/cavium/dev/octeon_powreg.h
128
#define POW_BIST_STAT UINT64_C(0x00016700000003f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
130
#define POW_BASE UINT64_C(0x0001670000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
131
#define POW_SIZE UINT64_C(0x400)
sys/arch/mips/cavium/dev/octeon_powreg.h
133
#define POW_PP_GRP_MSK_OFFSET(core) (UINT64_C(0) + (core) * 8)
sys/arch/mips/cavium/dev/octeon_powreg.h
134
#define POW_WQ_INT_THR0_OFFSET UINT64_C(0x80)
sys/arch/mips/cavium/dev/octeon_powreg.h
135
#define POW_WQ_INT_THR1_OFFSET UINT64_C(0x88)
sys/arch/mips/cavium/dev/octeon_powreg.h
136
#define POW_WQ_INT_THR2_OFFSET UINT64_C(0x90)
sys/arch/mips/cavium/dev/octeon_powreg.h
137
#define POW_WQ_INT_THR3_OFFSET UINT64_C(0x98)
sys/arch/mips/cavium/dev/octeon_powreg.h
138
#define POW_WQ_INT_THR4_OFFSET UINT64_C(0xa0)
sys/arch/mips/cavium/dev/octeon_powreg.h
139
#define POW_WQ_INT_THR5_OFFSET UINT64_C(0xa8)
sys/arch/mips/cavium/dev/octeon_powreg.h
140
#define POW_WQ_INT_THR6_OFFSET UINT64_C(0xb0)
sys/arch/mips/cavium/dev/octeon_powreg.h
141
#define POW_WQ_INT_THR7_OFFSET UINT64_C(0xb8)
sys/arch/mips/cavium/dev/octeon_powreg.h
142
#define POW_WQ_INT_THR8_OFFSET UINT64_C(0xc0)
sys/arch/mips/cavium/dev/octeon_powreg.h
143
#define POW_WQ_INT_THR9_OFFSET UINT64_C(0xc8)
sys/arch/mips/cavium/dev/octeon_powreg.h
144
#define POW_WQ_INT_THR10_OFFSET UINT64_C(0xd0)
sys/arch/mips/cavium/dev/octeon_powreg.h
145
#define POW_WQ_INT_THR11_OFFSET UINT64_C(0xd8)
sys/arch/mips/cavium/dev/octeon_powreg.h
146
#define POW_WQ_INT_THR12_OFFSET UINT64_C(0xe0)
sys/arch/mips/cavium/dev/octeon_powreg.h
147
#define POW_WQ_INT_THR13_OFFSET UINT64_C(0xe8)
sys/arch/mips/cavium/dev/octeon_powreg.h
148
#define POW_WQ_INT_THR14_OFFSET UINT64_C(0xf0)
sys/arch/mips/cavium/dev/octeon_powreg.h
149
#define POW_WQ_INT_THR15_OFFSET UINT64_C(0xf8)
sys/arch/mips/cavium/dev/octeon_powreg.h
150
#define POW_WQ_INT_CNT0_OFFSET UINT64_C(0x100)
sys/arch/mips/cavium/dev/octeon_powreg.h
151
#define POW_WQ_INT_CNT1_OFFSET UINT64_C(0x108)
sys/arch/mips/cavium/dev/octeon_powreg.h
152
#define POW_WQ_INT_CNT2_OFFSET UINT64_C(0x110)
sys/arch/mips/cavium/dev/octeon_powreg.h
153
#define POW_WQ_INT_CNT3_OFFSET UINT64_C(0x118)
sys/arch/mips/cavium/dev/octeon_powreg.h
154
#define POW_WQ_INT_CNT4_OFFSET UINT64_C(0x120)
sys/arch/mips/cavium/dev/octeon_powreg.h
155
#define POW_WQ_INT_CNT5_OFFSET UINT64_C(0x128)
sys/arch/mips/cavium/dev/octeon_powreg.h
156
#define POW_WQ_INT_CNT6_OFFSET UINT64_C(0x130)
sys/arch/mips/cavium/dev/octeon_powreg.h
157
#define POW_WQ_INT_CNT7_OFFSET UINT64_C(0x138)
sys/arch/mips/cavium/dev/octeon_powreg.h
158
#define POW_WQ_INT_CNT8_OFFSET UINT64_C(0x140)
sys/arch/mips/cavium/dev/octeon_powreg.h
159
#define POW_WQ_INT_CNT9_OFFSET UINT64_C(0x148)
sys/arch/mips/cavium/dev/octeon_powreg.h
160
#define POW_WQ_INT_CNT10_OFFSET UINT64_C(0x150)
sys/arch/mips/cavium/dev/octeon_powreg.h
161
#define POW_WQ_INT_CNT11_OFFSET UINT64_C(0x158)
sys/arch/mips/cavium/dev/octeon_powreg.h
162
#define POW_WQ_INT_CNT12_OFFSET UINT64_C(0x160)
sys/arch/mips/cavium/dev/octeon_powreg.h
163
#define POW_WQ_INT_CNT13_OFFSET UINT64_C(0x168)
sys/arch/mips/cavium/dev/octeon_powreg.h
164
#define POW_WQ_INT_CNT14_OFFSET UINT64_C(0x170)
sys/arch/mips/cavium/dev/octeon_powreg.h
165
#define POW_WQ_INT_CNT15_OFFSET UINT64_C(0x178)
sys/arch/mips/cavium/dev/octeon_powreg.h
166
#define POW_QOS_THR0_OFFSET UINT64_C(0x180)
sys/arch/mips/cavium/dev/octeon_powreg.h
167
#define POW_QOS_THR1_OFFSET UINT64_C(0x188)
sys/arch/mips/cavium/dev/octeon_powreg.h
168
#define POW_QOS_THR2_OFFSET UINT64_C(0x190)
sys/arch/mips/cavium/dev/octeon_powreg.h
169
#define POW_QOS_THR3_OFFSET UINT64_C(0x198)
sys/arch/mips/cavium/dev/octeon_powreg.h
170
#define POW_QOS_THR4_OFFSET UINT64_C(0x1a0)
sys/arch/mips/cavium/dev/octeon_powreg.h
171
#define POW_QOS_THR5_OFFSET UINT64_C(0x1a8)
sys/arch/mips/cavium/dev/octeon_powreg.h
172
#define POW_QOS_THR6_OFFSET UINT64_C(0x1b0)
sys/arch/mips/cavium/dev/octeon_powreg.h
173
#define POW_QOS_THR7_OFFSET UINT64_C(0x1b8)
sys/arch/mips/cavium/dev/octeon_powreg.h
174
#define POW_QOS_RND0_OFFSET UINT64_C(0x1c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
175
#define POW_QOS_RND1_OFFSET UINT64_C(0x1c8)
sys/arch/mips/cavium/dev/octeon_powreg.h
176
#define POW_QOS_RND2_OFFSET UINT64_C(0x1d0)
sys/arch/mips/cavium/dev/octeon_powreg.h
177
#define POW_QOS_RND3_OFFSET UINT64_C(0x1d8)
sys/arch/mips/cavium/dev/octeon_powreg.h
178
#define POW_QOS_RND4_OFFSET UINT64_C(0x1e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
179
#define POW_QOS_RND5_OFFSET UINT64_C(0x1e8)
sys/arch/mips/cavium/dev/octeon_powreg.h
180
#define POW_QOS_RND6_OFFSET UINT64_C(0x1f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
181
#define POW_QOS_RND7_OFFSET UINT64_C(0x1f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
182
#define POW_WQ_INT_OFFSET UINT64_C(0x200)
sys/arch/mips/cavium/dev/octeon_powreg.h
183
#define POW_WQ_INT_PC_OFFSET UINT64_C(0x208)
sys/arch/mips/cavium/dev/octeon_powreg.h
184
#define POW_NW_TIM_OFFSET UINT64_C(0x210)
sys/arch/mips/cavium/dev/octeon_powreg.h
185
#define POW_ECC_ERR_OFFSET UINT64_C(0x218)
sys/arch/mips/cavium/dev/octeon_powreg.h
186
#define POW_NOS_CNT_OFFSET UINT64_C(0x220)
sys/arch/mips/cavium/dev/octeon_powreg.h
187
#define POW_WS_PC0_OFFSET UINT64_C(0x280)
sys/arch/mips/cavium/dev/octeon_powreg.h
188
#define POW_WS_PC1_OFFSET UINT64_C(0x288)
sys/arch/mips/cavium/dev/octeon_powreg.h
189
#define POW_WS_PC2_OFFSET UINT64_C(0x290)
sys/arch/mips/cavium/dev/octeon_powreg.h
190
#define POW_WS_PC3_OFFSET UINT64_C(0x298)
sys/arch/mips/cavium/dev/octeon_powreg.h
191
#define POW_WS_PC4_OFFSET UINT64_C(0x2a0)
sys/arch/mips/cavium/dev/octeon_powreg.h
192
#define POW_WS_PC5_OFFSET UINT64_C(0x2a8)
sys/arch/mips/cavium/dev/octeon_powreg.h
193
#define POW_WS_PC6_OFFSET UINT64_C(0x2b0)
sys/arch/mips/cavium/dev/octeon_powreg.h
194
#define POW_WS_PC7_OFFSET UINT64_C(0x2b8)
sys/arch/mips/cavium/dev/octeon_powreg.h
195
#define POW_WS_PC8_OFFSET UINT64_C(0x2c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
196
#define POW_WS_PC9_OFFSET UINT64_C(0x2c8)
sys/arch/mips/cavium/dev/octeon_powreg.h
197
#define POW_WS_PC10_OFFSET UINT64_C(0x2d0)
sys/arch/mips/cavium/dev/octeon_powreg.h
198
#define POW_WS_PC11_OFFSET UINT64_C(0x2d8)
sys/arch/mips/cavium/dev/octeon_powreg.h
199
#define POW_WS_PC12_OFFSET UINT64_C(0x2e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
200
#define POW_WS_PC13_OFFSET UINT64_C(0x2e8)
sys/arch/mips/cavium/dev/octeon_powreg.h
201
#define POW_WS_PC14_OFFSET UINT64_C(0x2f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
202
#define POW_WS_PC15_OFFSET UINT64_C(0x2f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
203
#define POW_WA_PC0_OFFSET UINT64_C(0x300)
sys/arch/mips/cavium/dev/octeon_powreg.h
204
#define POW_WA_PC1_OFFSET UINT64_C(0x308)
sys/arch/mips/cavium/dev/octeon_powreg.h
205
#define POW_WA_PC2_OFFSET UINT64_C(0x310)
sys/arch/mips/cavium/dev/octeon_powreg.h
206
#define POW_WA_PC3_OFFSET UINT64_C(0x318)
sys/arch/mips/cavium/dev/octeon_powreg.h
207
#define POW_WA_PC4_OFFSET UINT64_C(0x320)
sys/arch/mips/cavium/dev/octeon_powreg.h
208
#define POW_WA_PC5_OFFSET UINT64_C(0x328)
sys/arch/mips/cavium/dev/octeon_powreg.h
209
#define POW_WA_PC6_OFFSET UINT64_C(0x330)
sys/arch/mips/cavium/dev/octeon_powreg.h
210
#define POW_WA_PC7_OFFSET UINT64_C(0x338)
sys/arch/mips/cavium/dev/octeon_powreg.h
211
#define POW_IQ_CNT0_OFFSET UINT64_C(0x340)
sys/arch/mips/cavium/dev/octeon_powreg.h
212
#define POW_IQ_CNT1_OFFSET UINT64_C(0x348)
sys/arch/mips/cavium/dev/octeon_powreg.h
213
#define POW_IQ_CNT2_OFFSET UINT64_C(0x350)
sys/arch/mips/cavium/dev/octeon_powreg.h
214
#define POW_IQ_CNT3_OFFSET UINT64_C(0x358)
sys/arch/mips/cavium/dev/octeon_powreg.h
215
#define POW_IQ_CNT4_OFFSET UINT64_C(0x360)
sys/arch/mips/cavium/dev/octeon_powreg.h
216
#define POW_IQ_CNT5_OFFSET UINT64_C(0x368)
sys/arch/mips/cavium/dev/octeon_powreg.h
217
#define POW_IQ_CNT6_OFFSET UINT64_C(0x370)
sys/arch/mips/cavium/dev/octeon_powreg.h
218
#define POW_IQ_CNT7_OFFSET UINT64_C(0x378)
sys/arch/mips/cavium/dev/octeon_powreg.h
219
#define POW_WA_COM_PC_OFFSET UINT64_C(0x380)
sys/arch/mips/cavium/dev/octeon_powreg.h
220
#define POW_IQ_COM_CNT_OFFSET UINT64_C(0x388)
sys/arch/mips/cavium/dev/octeon_powreg.h
221
#define POW_TS_PC_OFFSET UINT64_C(0x390)
sys/arch/mips/cavium/dev/octeon_powreg.h
222
#define POW_DS_PC_OFFSET UINT64_C(0x398)
sys/arch/mips/cavium/dev/octeon_powreg.h
223
#define POW_BIST_STAT_OFFSET UINT64_C(0x3f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
227
#define POW_PP_GRP_MSKX_XXX_63_16 UINT64_C(0xffffffffffff0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
228
#define POW_PP_GRP_MSKX_GRP_MSK UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
230
#define POW_WQ_INT_THRX_XXX_63_29 UINT64_C(0xffffffffe0000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
231
#define POW_WQ_INT_THRX_TC_EN UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
232
#define POW_WQ_INT_THRX_TC_THR UINT64_C(0x000000000f000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
233
#define POW_WQ_INT_THRX_XXX_23_18 UINT64_C(0x0000000000fc0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
234
#define POW_WQ_INT_THRX_DS_THR UINT64_C(0x000000000003f000)
sys/arch/mips/cavium/dev/octeon_powreg.h
235
#define POW_WQ_INT_THRX_XXX_11_6 UINT64_C(0x0000000000000fc0)
sys/arch/mips/cavium/dev/octeon_powreg.h
236
#define POW_WQ_INT_THRX_IQ_THR UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_powreg.h
238
#define POW_WQ_INT_CNTX_XXX_63_28 UINT64_C(0xfffffffff0000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
239
#define POW_WQ_INT_CNTX_TC_CNT UINT64_C(0x000000000f000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
240
#define POW_WQ_INT_CNTX_XXX_23_18 UINT64_C(0x0000000000fc0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
241
#define POW_WQ_INT_CNTX_DS_CNT UINT64_C(0x000000000003f000)
sys/arch/mips/cavium/dev/octeon_powreg.h
242
#define POW_WQ_INT_CNTX_XXX_11_6 UINT64_C(0x0000000000000fc0)
sys/arch/mips/cavium/dev/octeon_powreg.h
243
#define POW_WQ_INT_CNTX_IQ_CNT UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_powreg.h
245
#define POW_QOS_THRX_XXX_63_55 UINT64_C(0xff80000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
246
#define POW_QOS_THRX_DES_CNT UINT64_C(0x007f000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
247
#define POW_QOS_THRX_XXX_47_43 UINT64_C(0x0000f80000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
248
#define POW_QOS_THRX_BUF_CNT UINT64_C(0x000007f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
249
#define POW_QOS_THRX_XXX_35_31 UINT64_C(0x0000000f80000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
250
#define POW_QOS_THRX_FREE_CNT UINT64_C(0x000000007f000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
251
#define POW_QOS_THRX_XXX_23_18 UINT64_C(0x0000000000fc0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
252
#define POW_QOS_THRX_MAX_THR UINT64_C(0x000000000003f000)
sys/arch/mips/cavium/dev/octeon_powreg.h
253
#define POW_QOS_THRX_XXX_11_6 UINT64_C(0x0000000000000fc0)
sys/arch/mips/cavium/dev/octeon_powreg.h
254
#define POW_QOS_THRX_MIN_THR UINT64_C(0x000000000000003f)
sys/arch/mips/cavium/dev/octeon_powreg.h
256
#define POW_QOS_RNDX_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
257
#define POW_QOS_RNDX_RND_P3 UINT64_C(0x00000000ff000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
258
#define POW_QOS_RNDX_RND_P2 UINT64_C(0x0000000000ff0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
259
#define POW_QOS_RNDX_RND_P1 UINT64_C(0x000000000000ff00)
sys/arch/mips/cavium/dev/octeon_powreg.h
260
#define POW_QOS_RNDX_RND UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_powreg.h
262
#define POW_WQ_INT_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
263
#define POW_WQ_INT_IQ_DIS UINT64_C(0x00000000ffff0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
264
#define POW_WQ_INT_WQ_INT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
266
#define POW_WQ_INT_PC_XXX_63_60 UINT64_C(0xf000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
267
#define POW_WQ_INT_PC_PC UINT64_C(0x0fffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
268
#define POW_WQ_INT_PC_XXX_31_28 UINT64_C(0x00000000f0000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
269
#define POW_WQ_INT_PC_PC_THR UINT64_C(0x000000000fffff00)
sys/arch/mips/cavium/dev/octeon_powreg.h
270
#define POW_WQ_INT_PC_XXX_7_0 UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_powreg.h
272
#define POW_NW_TIM_XXX_63_10 UINT64_C(0xfffffffffffffc00)
sys/arch/mips/cavium/dev/octeon_powreg.h
273
#define POW_NW_TIM_NW_TIM UINT64_C(0x00000000000003ff)
sys/arch/mips/cavium/dev/octeon_powreg.h
275
#define POW_ECC_ERR_XXX_63_45 UINT64_C(0xffffe00000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
276
#define POW_ECC_ERR_IOP_IE UINT64_C(0x00001fff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
277
#define POW_ECC_ERR_XXX_31_29 UINT64_C(0x00000000e0000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
278
#define POW_ECC_ERR_IOP UINT64_C(0x000000001fff0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
292
#define POW_ECC_ERR_XXX_15_14 UINT64_C(0x000000000000c000)
sys/arch/mips/cavium/dev/octeon_powreg.h
293
#define POW_ECC_ERR_RPE_IE UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_powreg.h
294
#define POW_ECC_ERR_RPE UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_powreg.h
295
#define POW_ECC_ERR_XXX_11_9 UINT64_C(0x0000000000000e00)
sys/arch/mips/cavium/dev/octeon_powreg.h
296
#define POW_ECC_ERR_SYN UINT64_C(0x00000000000001f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
297
#define POW_ECC_ERR_DBE_IE UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
298
#define POW_ECC_ERR_SBE_IE UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_powreg.h
299
#define POW_ECC_ERR_DBE UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_powreg.h
300
#define POW_ECC_ERR_SBE UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_powreg.h
302
#define POW_NOS_CNT_XXX_63_7 UINT64_C(0xffffffffffffff80)
sys/arch/mips/cavium/dev/octeon_powreg.h
303
#define POW_NOS_CNT_NOS_CNT UINT64_C(0x000000000000007f)
sys/arch/mips/cavium/dev/octeon_powreg.h
305
#define POW_WS_PC0_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
306
#define POW_WS_PC0_WS_PC UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
308
#define POW_WA_PC0_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
309
#define POW_WA_PC0_WA_PC UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
311
#define POW_IQ_CNT0_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
312
#define POW_IQ_CNT0_IQ_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
314
#define POW_WA_COM_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
315
#define POW_WA_COM_PC_WA_PC UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
317
#define POW_WQ_COM_CNT_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
318
#define POW_WQ_COM_CNT_IQ_CNT UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
320
#define POW_TS_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
321
#define POW_TS_PC_TS_PC UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
323
#define POW_DS_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
324
#define POW_DS_PC_DS_PC UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
326
#define POW_BIST_STAT_XXX_63_7 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_powreg.h
327
#define POW_BIST_STAT_PP UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_powreg.h
328
#define POW_BIST_STAT_XXX_15_9 UINT64_C(0x000000000000fe00)
sys/arch/mips/cavium/dev/octeon_powreg.h
329
#define POW_BIST_STAT_CAM UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_powreg.h
330
#define POW_BIST_STAT_NBT1 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_powreg.h
331
#define POW_BIST_STAT_NBT0 UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_powreg.h
332
#define POW_BIST_STAT_IDX UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_powreg.h
333
#define POW_BIST_STAT_FIDX UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_powreg.h
334
#define POW_BIST_STAT_NBR1 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
335
#define POW_BIST_STAT_NBR0 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_powreg.h
336
#define POW_BIST_STAT_PEND UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_powreg.h
337
#define POW_BIST_STAT_ADR UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_powreg.h
345
#define POW_GET_WORK_LOAD_WAIT UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
349
#define POW_STATUS_LOAD_COREID UINT64_C(0x00000000000003c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
350
#define POW_STATUS_LOAD_GET_REV UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_powreg.h
351
#define POW_STATUS_LOAD_GET_CUR UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_powreg.h
352
#define POW_STATUS_LOAD_GET_WQP UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
353
#define POW_STATUS_LOAD_GET_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_powreg.h
356
#define POW_STATUS_LOAD_RESULT_PEND_TAG_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
357
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
358
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH_FULL UINT64_C(0x1000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
359
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_SWITCH_NULL UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
360
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_DESCHED UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
361
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_DESCHED_SWITCH UINT64_C(0x0200000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
362
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NOSCHED UINT64_C(0x0100000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
363
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NEW_WORK UINT64_C(0x0080000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
364
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NEW_WORK_WAIT UINT64_C(0x0040000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
365
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NULL_RD UINT64_C(0x0020000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
366
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_NOSCHED_CLR UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
367
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_XXX_51 UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
368
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
369
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
370
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_XXX_35_34 UINT64_C(0x0000000c00000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
371
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TYPE UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
372
#define POW_STATUS_LOAD_RESULT_PEND_TAG_PEND_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
375
#define POW_STATUS_LOAD_RESULT_PEND_WQP_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
376
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
377
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH_FULL UINT64_C(0x1000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
378
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_SWITCH_NULL UINT64_C(0x0800000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
379
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_DESCHED UINT64_C(0x0400000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
38
#define POW_PP_GRP_MSK(core) (UINT64_C(0x0001670000000000) + (core) * 8)
sys/arch/mips/cavium/dev/octeon_powreg.h
380
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_DESCHED_SWITCH UINT64_C(0x0200000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
381
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NOSCHED UINT64_C(0x0100000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
382
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NEW_WORK UINT64_C(0x0080000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
383
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NEW_WORK_WAIT UINT64_C(0x0040000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
384
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NULL_RD UINT64_C(0x0020000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
385
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_NOSCHED_CLR UINT64_C(0x0010000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
386
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_XXX_51 UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
387
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
388
#define POW_STATUS_LOAD_RESULT_PEND_WQP_PEND_WQP UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
39
#define POW_WQ_INT_THR0 UINT64_C(0x0001670000000080)
sys/arch/mips/cavium/dev/octeon_powreg.h
391
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
392
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_LINK_INDEX UINT64_C(0x3ff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
393
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
394
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
395
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_HEAD UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
396
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAIL UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
397
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG_TYPE UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
398
#define POW_STATUS_LOAD_RESULT_CUR_TAG_NEXT_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
40
#define POW_WQ_INT_THR1 UINT64_C(0x0001670000000088)
sys/arch/mips/cavium/dev/octeon_powreg.h
401
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
402
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_REVLINK_INDEX UINT64_C(0x3ff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
403
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
404
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
405
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_HEAD UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
406
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAIL UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
407
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG_TYPE UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
408
#define POW_STATUS_LOAD_RESULT_CUR_TAG_PREV_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
41
#define POW_WQ_INT_THR2 UINT64_C(0x0001670000000090)
sys/arch/mips/cavium/dev/octeon_powreg.h
411
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
412
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_LINK_INDEX UINT64_C(0x3ff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
413
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
414
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
415
#define POW_STATUS_LOAD_RESULT_CUR_WQP_NEXT_WQP UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
418
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_XXX_63_62 UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
419
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_REVLINK_INDEX UINT64_C(0x3ff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
42
#define POW_WQ_INT_THR3 UINT64_C(0x0001670000000098)
sys/arch/mips/cavium/dev/octeon_powreg.h
420
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
421
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
422
#define POW_STATUS_LOAD_RESULT_CUR_WQP_PREV_WQP UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
426
#define POW_MEMORY_LOAD_INDEX UINT64_C(0x000000000000ffe0)
sys/arch/mips/cavium/dev/octeon_powreg.h
427
#define POW_MEMORY_LOAD_GET_DES UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_powreg.h
428
#define POW_MEMORY_LOAD_GET_WQP UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
429
#define POW_MEMORY_LOAD_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_powreg.h
43
#define POW_WQ_INT_THR4 UINT64_C(0x00016700000000a0)
sys/arch/mips/cavium/dev/octeon_powreg.h
432
#define POW_MEMORY_LOAD_RESULT_TAG_XXX_63_51 UINT64_C(0xfff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
433
#define POW_MEMORY_LOAD_RESULT_TAG_NEXT_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
434
#define POW_MEMORY_LOAD_RESULT_TAG_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
435
#define POW_MEMORY_LOAD_RESULT_TAG_XXX_35 UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
436
#define POW_MEMORY_LOAD_RESULT_TAG_TAIL UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
437
#define POW_MEMORY_LOAD_RESULT_TAG_TAG_TYPE UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
438
#define POW_MEMORY_LOAD_RESULT_TAG_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
44
#define POW_WQ_INT_THR5 UINT64_C(0x00016700000000a8)
sys/arch/mips/cavium/dev/octeon_powreg.h
441
#define POW_MEMORY_LOAD_RESULT_WQP_XXX_63_51 UINT64_C(0xfff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
442
#define POW_MEMORY_LOAD_RESULT_WQP_NEXT_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
443
#define POW_MEMORY_LOAD_RESULT_WQP_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
444
#define POW_MEMORY_LOAD_RESULT_WQP_WQP UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
447
#define POW_MEMORY_LOAD_RESULT_DESCHED_XXX_63_51 UINT64_C(0xfff8000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
448
#define POW_MEMORY_LOAD_RESULT_DESCHED_FWD_INDEX UINT64_C(0x0007ff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
449
#define POW_MEMORY_LOAD_RESULT_DESCHED_GRP UINT64_C(0x000000f000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
45
#define POW_WQ_INT_THR6 UINT64_C(0x00016700000000b0)
sys/arch/mips/cavium/dev/octeon_powreg.h
450
#define POW_MEMORY_LOAD_RESULT_DESCHED_NOSCHED UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
451
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_SWITCH UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
452
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TYPE UINT64_C(0x0000000300000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
453
#define POW_MEMORY_LOAD_RESULT_DESCHED_PEND_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
458
#define POW_IDXPTR_LOAD_QOSGRP UINT64_C(0x00000000000001e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
459
#define POW_IDXPTR_LOAD_GET_DES_GET_TAIL UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_powreg.h
46
#define POW_WQ_INT_THR7 UINT64_C(0x00016700000000b8)
sys/arch/mips/cavium/dev/octeon_powreg.h
460
#define POW_IDXPTR_LOAD_GET_RMT UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
461
#define POW_IDXPTR_LOAD_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_powreg.h
464
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_63_52 UINT64_C(0xfff0000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
465
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_VAL UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
466
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_ONE UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
467
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_49 UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
468
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_HEAD UINT64_C(0x0001ffc000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
469
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_37 UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
47
#define POW_WQ_INT_THR8 UINT64_C(0x00016700000000c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
470
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_FREE_TAIL UINT64_C(0x0000001ffc000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
471
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_VAL UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
472
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_ONE UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
473
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_23 UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_powreg.h
474
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_HEAD UINT64_C(0x00000000007ff000)
sys/arch/mips/cavium/dev/octeon_powreg.h
475
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_powreg.h
476
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_LOC_TAIL UINT64_C(0x00000000000007ff)
sys/arch/mips/cavium/dev/octeon_powreg.h
479
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_63_52 UINT64_C(0xfff0000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
48
#define POW_WQ_INT_THR9 UINT64_C(0x00016700000000c8)
sys/arch/mips/cavium/dev/octeon_powreg.h
480
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_VAL UINT64_C(0x0008000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
481
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_ONE UINT64_C(0x0004000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
482
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_49 UINT64_C(0x0002000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
483
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_HEAD UINT64_C(0x0001ffc000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
484
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_37 UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
485
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_NOSCHED_TAIL UINT64_C(0x0000001ffc000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
486
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_VAL UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
487
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_ONE UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
488
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_23 UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_powreg.h
489
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_HEAD UINT64_C(0x00000000007ff000)
sys/arch/mips/cavium/dev/octeon_powreg.h
49
#define POW_WQ_INT_THR10 UINT64_C(0x00016700000000d0)
sys/arch/mips/cavium/dev/octeon_powreg.h
490
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_XXX_11 UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_powreg.h
491
#define POW_IDXPTR_LOAD_RESULT_GRP_NOSCHED_DES_DES_TAIL UINT64_C(0x00000000000007ff)
sys/arch/mips/cavium/dev/octeon_powreg.h
494
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_XXX_63_39 UINT64_C(0xffffff8000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
495
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_IS_HEAD UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
496
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_VAL UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
497
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_ONE UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
498
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_HEAD_RMT_HEAD UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
50
#define POW_WQ_INT_THR11 UINT64_C(0x00016700000000d8)
sys/arch/mips/cavium/dev/octeon_powreg.h
501
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_XXX_63_39 UINT64_C(0xffffff8000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
502
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_IS_HEAD UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
503
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_VAL UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
504
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_ONE UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
505
#define POW_IDXPTR_LOAD_RESULT_QUEUE_REMOTE_TAIL_RMT_TAIL UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
509
#define POW_NULL_RD_LOAD_39_3 UINT64_C(0x000000fffffffff8)
sys/arch/mips/cavium/dev/octeon_powreg.h
51
#define POW_WQ_INT_THR12 UINT64_C(0x00016700000000e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
510
#define POW_NULL_RD_LOAD_2_0 UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_powreg.h
512
#define POW_NULL_RD_LOAD_RESULT_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_powreg.h
513
#define POW_NULL_RD_LOAD_RESULT_STATUS UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_powreg.h
52
#define POW_WQ_INT_THR13 UINT64_C(0x00016700000000e8)
sys/arch/mips/cavium/dev/octeon_powreg.h
522
#define POW_IOBDMA_GET_WORK_WAIT UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_powreg.h
524
#define POW_IOBDMA_GET_WORK_RESULT_NO_WORK UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
525
#define POW_IOBDMA_GET_WORK_RESULT_ADDR UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
529
#define POW_IOBDMA_NULL_RD_RESULT_STATUS UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_powreg.h
53
#define POW_WQ_INT_THR14 UINT64_C(0x00016700000000f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
537
#define POW_PHY_ADDR_STORE_ADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
539
#define POW_STORE_DATA_NO_SCHED UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
54
#define POW_WQ_INT_THR15 UINT64_C(0x00016700000000f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
540
#define POW_STORE_DATA_62_61 UINT64_C(0x6000000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
541
#define POW_STORE_DATA_INDEX UINT64_C(0x1fff000000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
542
#define POW_STORE_DATA_OP UINT64_C(0x0000f00000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
543
#define POW_STORE_DATA_43_42 UINT64_C(0x00000c0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
544
#define POW_STORE_DATA_QOS UINT64_C(0x0000038000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
545
#define POW_STORE_DATA_GRP UINT64_C(0x0000007800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
546
#define POW_STORE_DATA_TYPE UINT64_C(0x0000000700000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
547
#define POW_STORE_DATA_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
55
#define POW_WQ_INT_CNT0 UINT64_C(0x0001670000000100)
sys/arch/mips/cavium/dev/octeon_powreg.h
553
#define POW_WQE_WORD0_XXX_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
554
#define POW_WQE_WORD0_NEXT UINT64_C(0x000000ffffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
556
#define POW_WQE_WORD1_XXX_63_42 UINT64_C(0xfffffc0000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
557
#define POW_WQE_WORD1_QOS UINT64_C(0x0000038000000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
558
#define POW_WQE_WORD1_GRP UINT64_C(0x0000007800000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
559
#define POW_WQE_WORD1_TT UINT64_C(0x0000000700000000)
sys/arch/mips/cavium/dev/octeon_powreg.h
56
#define POW_WQ_INT_CNT1 UINT64_C(0x0001670000000108)
sys/arch/mips/cavium/dev/octeon_powreg.h
560
#define POW_WQE_WORD1_TAG UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_powreg.h
57
#define POW_WQ_INT_CNT2 UINT64_C(0x0001670000000110)
sys/arch/mips/cavium/dev/octeon_powreg.h
58
#define POW_WQ_INT_CNT3 UINT64_C(0x0001670000000118)
sys/arch/mips/cavium/dev/octeon_powreg.h
59
#define POW_WQ_INT_CNT4 UINT64_C(0x0001670000000120)
sys/arch/mips/cavium/dev/octeon_powreg.h
60
#define POW_WQ_INT_CNT5 UINT64_C(0x0001670000000128)
sys/arch/mips/cavium/dev/octeon_powreg.h
61
#define POW_WQ_INT_CNT6 UINT64_C(0x0001670000000130)
sys/arch/mips/cavium/dev/octeon_powreg.h
62
#define POW_WQ_INT_CNT7 UINT64_C(0x0001670000000138)
sys/arch/mips/cavium/dev/octeon_powreg.h
63
#define POW_WQ_INT_CNT8 UINT64_C(0x0001670000000140)
sys/arch/mips/cavium/dev/octeon_powreg.h
64
#define POW_WQ_INT_CNT9 UINT64_C(0x0001670000000148)
sys/arch/mips/cavium/dev/octeon_powreg.h
65
#define POW_WQ_INT_CNT10 UINT64_C(0x0001670000000150)
sys/arch/mips/cavium/dev/octeon_powreg.h
66
#define POW_WQ_INT_CNT11 UINT64_C(0x0001670000000158)
sys/arch/mips/cavium/dev/octeon_powreg.h
67
#define POW_WQ_INT_CNT12 UINT64_C(0x0001670000000160)
sys/arch/mips/cavium/dev/octeon_powreg.h
68
#define POW_WQ_INT_CNT13 UINT64_C(0x0001670000000168)
sys/arch/mips/cavium/dev/octeon_powreg.h
69
#define POW_WQ_INT_CNT14 UINT64_C(0x0001670000000170)
sys/arch/mips/cavium/dev/octeon_powreg.h
70
#define POW_WQ_INT_CNT15 UINT64_C(0x0001670000000178)
sys/arch/mips/cavium/dev/octeon_powreg.h
71
#define POW_QOS_THR0 UINT64_C(0x0001670000000180)
sys/arch/mips/cavium/dev/octeon_powreg.h
72
#define POW_QOS_THR1 UINT64_C(0x0001670000000188)
sys/arch/mips/cavium/dev/octeon_powreg.h
73
#define POW_QOS_THR2 UINT64_C(0x0001670000000190)
sys/arch/mips/cavium/dev/octeon_powreg.h
74
#define POW_QOS_THR3 UINT64_C(0x0001670000000198)
sys/arch/mips/cavium/dev/octeon_powreg.h
75
#define POW_QOS_THR4 UINT64_C(0x00016700000001a0)
sys/arch/mips/cavium/dev/octeon_powreg.h
76
#define POW_QOS_THR5 UINT64_C(0x00016700000001a8)
sys/arch/mips/cavium/dev/octeon_powreg.h
77
#define POW_QOS_THR6 UINT64_C(0x00016700000001b0)
sys/arch/mips/cavium/dev/octeon_powreg.h
78
#define POW_QOS_THR7 UINT64_C(0x00016700000001b8)
sys/arch/mips/cavium/dev/octeon_powreg.h
79
#define POW_QOS_RND0 UINT64_C(0x00016700000001c0)
sys/arch/mips/cavium/dev/octeon_powreg.h
80
#define POW_QOS_RND1 UINT64_C(0x00016700000001c8)
sys/arch/mips/cavium/dev/octeon_powreg.h
81
#define POW_QOS_RND2 UINT64_C(0x00016700000001d0)
sys/arch/mips/cavium/dev/octeon_powreg.h
82
#define POW_QOS_RND3 UINT64_C(0x00016700000001d8)
sys/arch/mips/cavium/dev/octeon_powreg.h
83
#define POW_QOS_RND4 UINT64_C(0x00016700000001e0)
sys/arch/mips/cavium/dev/octeon_powreg.h
84
#define POW_QOS_RND5 UINT64_C(0x00016700000001e8)
sys/arch/mips/cavium/dev/octeon_powreg.h
85
#define POW_QOS_RND6 UINT64_C(0x00016700000001f0)
sys/arch/mips/cavium/dev/octeon_powreg.h
86
#define POW_QOS_RND7 UINT64_C(0x00016700000001f8)
sys/arch/mips/cavium/dev/octeon_powreg.h
87
#define POW_WQ_INT UINT64_C(0x0001670000000200)
sys/arch/mips/cavium/dev/octeon_powreg.h
88
#define POW_WQ_INT_PC UINT64_C(0x0001670000000208)
sys/arch/mips/cavium/dev/octeon_powreg.h
89
#define POW_NW_TIM UINT64_C(0x0001670000000210)
sys/arch/mips/cavium/dev/octeon_powreg.h
90
#define POW_ECC_ERR UINT64_C(0x0001670000000218)
sys/arch/mips/cavium/dev/octeon_powreg.h
91
#define POW_NOS_CNT UINT64_C(0x0001670000000220)
sys/arch/mips/cavium/dev/octeon_powreg.h
92
#define POW_WS_PC0 UINT64_C(0x0001670000000280)
sys/arch/mips/cavium/dev/octeon_powreg.h
93
#define POW_WS_PC1 UINT64_C(0x0001670000000288)
sys/arch/mips/cavium/dev/octeon_powreg.h
94
#define POW_WS_PC2 UINT64_C(0x0001670000000290)
sys/arch/mips/cavium/dev/octeon_powreg.h
95
#define POW_WS_PC3 UINT64_C(0x0001670000000298)
sys/arch/mips/cavium/dev/octeon_powreg.h
96
#define POW_WS_PC4 UINT64_C(0x00016700000002a0)
sys/arch/mips/cavium/dev/octeon_powreg.h
97
#define POW_WS_PC5 UINT64_C(0x00016700000002a8)
sys/arch/mips/cavium/dev/octeon_powreg.h
98
#define POW_WS_PC6 UINT64_C(0x00016700000002b0)
sys/arch/mips/cavium/dev/octeon_powreg.h
99
#define POW_WS_PC7 UINT64_C(0x00016700000002b8)
sys/arch/mips/cavium/dev/octeon_rnm.c
166
uint64_t bist_status, sample, expected = UINT64_C(0xd654ff35fadf866b);
sys/arch/mips/cavium/dev/octeon_rnmreg.h
42
#define RNM_CTL_STATUS UINT64_C(0x0001180040000000)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
43
#define RNM_BIST_STATUS UINT64_C(0x0001180040000008)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
47
#define RNM_CTL_STATUS_XXX_63_5 UINT64_C(0xfffffffffffffe00)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
48
#define RNM_CTL_STATUS_ENT_SEL_MASK UINT64_C(0x00000000000001e0)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
49
#define RNM_CTL_STATUS_EXP_ENT UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
50
#define RNM_CTL_STATUS_RNG_RST UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
51
#define RNM_CTL_STATUS_RNM_RST UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
52
#define RNM_CTL_STATUS_RNG_EN UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
53
#define RNM_CTL_STATUS_ENT_EN UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
55
#define RNM_BIST_STATUS_XXX_63_2 UINT64_C(0xfffffffffffffffc)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
56
#define RNM_BIST_STATUS_RRC UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_rnmreg.h
57
#define RNM_BIST_STATUS_MEM UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_smireg.h
48
#define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000)
sys/arch/mips/cavium/dev/octeon_smireg.h
49
#define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_smireg.h
52
#define SMI_CMD_15_13 UINT64_C(0x000000000000e000)
sys/arch/mips/cavium/dev/octeon_smireg.h
53
#define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00)
sys/arch/mips/cavium/dev/octeon_smireg.h
54
#define SMI_CMD_7_5 UINT64_C(0x00000000000000e0)
sys/arch/mips/cavium/dev/octeon_smireg.h
55
#define SMI_CMD_REG_ADR UINT64_C(0x000000000000001f)
sys/arch/mips/cavium/dev/octeon_smireg.h
58
#define SMI_WR_DAT_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_smireg.h
59
#define SMI_WR_DAT_PENDING UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_smireg.h
60
#define SMI_WR_DAT_VAL UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_smireg.h
61
#define SMI_WR_DAT_DAT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_smireg.h
64
#define SMI_RD_DAT_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_smireg.h
65
#define SMI_RD_DAT_PENDING UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_smireg.h
66
#define SMI_RD_DAT_VAL UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_smireg.h
67
#define SMI_RD_DAT_DAT UINT64_C(0x000000000000ffff)
sys/arch/mips/cavium/dev/octeon_smireg.h
70
#define SMI_CLK_63_21 UINT64_C(0xffffffffffe00000)
sys/arch/mips/cavium/dev/octeon_smireg.h
71
#define SMI_CLK_SAMPLE_HI UINT64_C(0x00000000001f0000)
sys/arch/mips/cavium/dev/octeon_smireg.h
72
#define SMI_CLK_15_14 UINT64_C(0x000000000000c000)
sys/arch/mips/cavium/dev/octeon_smireg.h
73
#define SMI_CLK_CLK_IDLE UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_smireg.h
74
#define SMI_CLK_PREAMBLE UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_smireg.h
75
#define SMI_CLK_SAMPLE UINT64_C(0x0000000000000f00)
sys/arch/mips/cavium/dev/octeon_smireg.h
76
#define SMI_CLK_PHASE UINT64_C(0x00000000000000ff)
sys/arch/mips/cavium/dev/octeon_smireg.h
79
#define SMI_EN_63_1 UINT64_C(0xfffffffffffffffe)
sys/arch/mips/cavium/dev/octeon_smireg.h
80
#define SMI_EN_EN UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_twsireg.h
45
#define MIO_TWS_SW_TWSI_V UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
46
#define MIO_TWS_SW_TWSI_SLONLY UINT64_C(0x4000000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
47
#define MIO_TWS_SW_TWSI_EIA UINT64_C(0x2000000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
48
#define MIO_TWS_SW_TWSI_OP UINT64_C(0x1e00000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
55
#define MIO_TWS_SW_TWSI_R UINT64_C(0x0100000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
56
#define MIO_TWS_SW_TWSI_SOVR UINT64_C(0x0080000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
57
#define MIO_TWS_SW_TWSI_SIZE UINT64_C(0x0070000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
58
#define MIO_TWS_SW_TWSI_SCR UINT64_C(0x000c000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
59
#define MIO_TWS_SW_TWSI_A UINT64_C(0x0003ff0000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
60
#define MIO_TWS_SW_TWSI_IA UINT64_C(0x000000f800000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
61
#define MIO_TWS_SW_TWSI_EOP_IA UINT64_C(0x0000000700000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
69
#define MIO_TWS_SW_TWSI_D UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_twsireg.h
71
#define MIO_TWS_TWSI_SW_V UINT64_C(0xc000000000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
72
#define MIO_TWS_TWSI_SW_XXX_61_32 UINT64_C(0x3fffffff00000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
73
#define MIO_TWS_TWSI_SW_D UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_twsireg.h
75
#define MIO_TWS_INT_XXX_63_12 UINT64_C(0xfffffffffffff000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
76
#define MIO_TWS_INT_SCL UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_twsireg.h
77
#define MIO_TWS_INT_SDA UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_twsireg.h
78
#define MIO_TWS_INT_SCL_OVR UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_twsireg.h
79
#define MIO_TWS_INT_SDA_OVR UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_twsireg.h
80
#define MIO_TWS_INT_XXX_7 UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_twsireg.h
81
#define MIO_TWS_INT_CORE_EN UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_twsireg.h
82
#define MIO_TWS_INT_TS_EN UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_twsireg.h
83
#define MIO_TWS_INT_ST_EN UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_twsireg.h
84
#define MIO_TWS_INT_XXX_3 UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_twsireg.h
85
#define MIO_TWS_INT_CORE_INT UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_twsireg.h
86
#define MIO_TWS_INT_TS_INT UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_twsireg.h
87
#define MIO_TWS_INT_ST_INT UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_twsireg.h
89
#define MIO_TWS_SW_TWSI_EXT_XXX_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
90
#define MIO_TWS_SW_TWSI_EXT_IA UINT64_C(0x000000ff00000000)
sys/arch/mips/cavium/dev/octeon_twsireg.h
91
#define MIO_TWS_SW_TWSI_EXT_D UINT64_C(0x00000000ffffffff)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
100
#define USBN_INT_NR_PU_F UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
101
#define USBN_INT_NR_PO_E UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
102
#define USBN_INT_PR_PU_F UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
103
#define USBN_INT_PR_PO_E UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
105
#define USBN_CLK_CTL_XXX_63_18 UINT64_C(0xfffffffffffc0000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
106
#define USBN_CLK_CTL_HCLK_RST UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
107
#define USBN_CLK_CTL_P_X_ON UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
108
#define USBN_CLK_CTL_P_RCLK UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
109
#define USBN_CLK_CTL_P_XENBN UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
110
#define USBN_CLK_CTL_P_COM_ON UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
111
#define USBN_CLK_CTL_P_C_SEL UINT64_C(0x0000000000001800)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
115
#define USBN_CLK_CTL_CDIV_BYP UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
116
#define USBN_CLK_CTL_SD_MODE UINT64_C(0x0000000000000300)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
117
#define USBN_CLK_CTL_S_BIST UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
118
#define USBN_CLK_CTL_POR UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
119
#define USBN_CLK_CTL_ENABLE UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
120
#define USBN_CLK_CTL_PRST UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
121
#define USBN_CLK_CTL_HRST UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
122
#define USBN_CLK_CTL_DIVIDE UINT64_C(0x0000000000000007)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
124
#define USBN_CLK_CTL_DIVIDE2 UINT64_C(0x00000000000c0000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
125
#define USBN_CLK_CTL_P_RTYPE UINT64_C(0x000000000000c000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
127
#define USBN_USBP_CTL_STATUS_XXX_63_38 UINT64_C(0xffffffc000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
128
#define USBN_USBP_CTL_STATUS_BIST_DONE UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
129
#define USBN_USBP_CTL_STATUS_BIST_ERR UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
130
#define USBN_USBP_CTL_STATUS_TDATA_OUT UINT64_C(0x0000000f00000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
131
#define USBN_USBP_CTL_STATUS_SPARES UINT64_C(0x00000000e0000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
132
#define USBN_USBP_CTL_STATUS_USBC_END UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
133
#define USBN_USBP_CTL_STATUS_USBP_BIST UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
134
#define USBN_USBP_CTL_STATUS_TCLK UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
135
#define USBN_USBP_CTL_STATUS_DP_PULLD UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
136
#define USBN_USBP_CTL_STATUS_DM_PULLD UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
137
#define USBN_USBP_CTL_STATUS_HST_MODE UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
138
#define USBN_USBP_CTL_STATUS_TUNING UINT64_C(0x0000000000780000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
139
#define USBN_USBP_CTL_STATUS_TX_BS_ENH UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
140
#define USBN_USBP_CTL_STATUS_TX_BS_EN UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
141
#define USBN_USBP_CTL_STATUS_LOOP_ENB UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
142
#define USBN_USBP_CTL_STATUS_VTEST_ENB UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
143
#define USBN_USBP_CTL_STATUS_BIST_ENB UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
144
#define USBN_USBP_CTL_STATUS_TDATA_SEL UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
145
#define USBN_USBP_CTL_STATUS_TADDR_IN UINT64_C(0x0000000000001e00)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
146
#define USBN_USBP_CTL_STATUS_TDATA_IN UINT64_C(0x00000000000001fe)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
147
#define USBN_USBP_CTL_STATUS_ATE_RESET UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
149
#define USBN_USBP_CTL_STATUS_TXRISETUNE UINT64_C(0x8000000000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
150
#define USBN_USBP_CTL_STATUS_TXVREFTUNE UINT64_C(0x7800000000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
151
#define USBN_USBP_CTL_STATUS_TXFSLSTUNE UINT64_C(0x0780000000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
152
#define USBN_USBP_CTL_STATUS_TXHSXVTUNE UINT64_C(0x0060000000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
153
#define USBN_USBP_CTL_STATUS_SQRXTUNE UINT64_C(0x001c000000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
154
#define USBN_USBP_CTL_STATUS_COMPDISTUNE UINT64_C(0x0003800000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
155
#define USBN_USBP_CTL_STATUS_OTGTUNE UINT64_C(0x0000700000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
156
#define USBN_USBP_CTL_STATUS_OTGDISABLE UINT64_C(0x0000080000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
157
#define USBN_USBP_CTL_STATUS_PORTRESET UINT64_C(0x0000040000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
158
#define USBN_USBP_CTL_STATUS_DRVVBUS UINT64_C(0x0000020000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
159
#define USBN_USBP_CTL_STATUS_LSBIST UINT64_C(0x0000010000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
160
#define USBN_USBP_CTL_STATUS_FSBIST UINT64_C(0x0000008000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
161
#define USBN_USBP_CTL_STATUS_HSBIST UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
163
#define USBN_BIST_STATUS_XXX_63_3 UINT64_C(0xfffffffffffffff8)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
164
#define USBN_BIST_STATUS_USBC_BIS UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
165
#define USBN_BIST_STATUS_NIF_BIS UINT64_C(0x0000000000000002)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
166
#define USBN_BIST_STATUS_NOF_BIS UINT64_C(0x0000000000000001)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
168
#define USBN_BIST_STATUS_U2NC_BIS UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
169
#define USBN_BIST_STATUS_U2NF_BIS UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
170
#define USBN_BIST_STATUS_E2HC_BIS UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
171
#define USBN_BIST_STATUS_N2UF_BIS UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
173
#define USBN_CTL_STATUS_XXX_63_6 UINT64_C(0xffffffffffffffc0)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
174
#define USBN_CTL_STATUS_DMA_0PAG UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
175
#define USBN_CTL_STATUS_DMA_STT UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
176
#define USBN_CTL_STATUS_DMA_TEST UINT64_C(0x0000000000000008)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
177
#define USBN_CTL_STATUS_INV_A2 UINT64_C(0x0000000000000004)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
178
#define USBN_CTL_STATUS_L2C_EMOD UINT64_C(0x0000000000000003)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
180
#define USBN_DMA_TEST_XXX_63_40 UINT64_C(0xffffff0000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
181
#define USBN_DMA_TEST_DONE UINT64_C(0x0000008000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
182
#define USBN_DMA_TEST_REQ UINT64_C(0x0000004000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
183
#define USBN_DMA_TEST_F_ADDR UINT64_C(0x0000003ffff00000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
184
#define USBN_DMA_TEST_COUNT UINT64_C(0x00000000000ffe00)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
185
#define USBN_DMA_TEST_CHANNEL UINT64_C(0x00000000000001f0)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
186
#define USBN_DMA_TEST_BURST UINT64_C(0x000000000000000f)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
189
#define USBN_DMA0_INB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
190
#define USBN_DMA0_INB_CHNX_ADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
193
#define USBN_DMA0_OUTB_CHNX_XXX_63_36 UINT64_C(0xfffffff000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
194
#define USBN_DMA0_OUTB_CHNX_ADDR UINT64_C(0x0000000fffffffff)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
65
#define USBN_INT_XXX_63_38 UINT64_C(0xffffffc000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
66
#define USBN_INT_ND4O_DPF UINT64_C(0x0000002000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
67
#define USBN_INT_ND4O_DPE UINT64_C(0x0000001000000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
68
#define USBN_INT_ND4O_RPF UINT64_C(0x0000000800000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
69
#define USBN_INT_ND4O_RPE UINT64_C(0x0000000400000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
70
#define USBN_INT_LTL_F_PF UINT64_C(0x0000000200000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
71
#define USBN_INT_LTL_F_PE UINT64_C(0x0000000100000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
72
#define USBN_INT_U2N_C_PE UINT64_C(0x0000000080000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
73
#define USBN_INT_U2N_C_PF UINT64_C(0x0000000040000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
74
#define USBN_INT_U2N_D_PF UINT64_C(0x0000000020000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
75
#define USBN_INT_U2N_D_PE UINT64_C(0x0000000010000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
76
#define USBN_INT_N2U_PE UINT64_C(0x0000000008000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
77
#define USBN_INT_N2U_PF UINT64_C(0x0000000004000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
78
#define USBN_INT_UOD_PF UINT64_C(0x0000000002000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
79
#define USBN_INT_UOD_PE UINT64_C(0x0000000001000000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
80
#define USBN_INT_RQ_Q3_E UINT64_C(0x0000000000800000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
81
#define USBN_INT_RQ_Q3_F UINT64_C(0x0000000000400000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
82
#define USBN_INT_RQ_Q2_E UINT64_C(0x0000000000200000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
83
#define USBN_INT_RQ_Q2_F UINT64_C(0x0000000000100000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
84
#define USBN_INT_RG_FI_F UINT64_C(0x0000000000080000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
85
#define USBN_INT_RG_FI_E UINT64_C(0x0000000000040000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
86
#define USBN_INT_LT_FI_F UINT64_C(0x0000000000020000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
87
#define USBN_INT_LT_FI_E UINT64_C(0x0000000000010000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
88
#define USBN_INT_L2C_A_F UINT64_C(0x0000000000008000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
89
#define USBN_INT_L2C_S_E UINT64_C(0x0000000000004000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
90
#define USBN_INT_DCRED_F UINT64_C(0x0000000000002000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
91
#define USBN_INT_DCRED_E UINT64_C(0x0000000000001000)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
92
#define USBN_INT_LT_PU_F UINT64_C(0x0000000000000800)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
93
#define USBN_INT_LT_PO_E UINT64_C(0x0000000000000400)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
94
#define USBN_INT_NT_PU_F UINT64_C(0x0000000000000200)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
95
#define USBN_INT_NT_PO_E UINT64_C(0x0000000000000100)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
96
#define USBN_INT_PT_PU_F UINT64_C(0x0000000000000080)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
97
#define USBN_INT_PT_PO_E UINT64_C(0x0000000000000040)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
98
#define USBN_INT_LR_PU_F UINT64_C(0x0000000000000020)
sys/arch/mips/cavium/dev/octeon_usbnreg.h
99
#define USBN_INT_LR_PO_E UINT64_C(0x0000000000000010)
sys/arch/mips/cavium/octeonreg.h
100
#define RST_OCX UINT64_C(0x1180006001618)
sys/arch/mips/cavium/octeonreg.h
101
#define RST_INT UINT64_C(0x1180006001628)
sys/arch/mips/cavium/octeonreg.h
102
#define RST_CKILL UINT64_C(0x1180006001638)
sys/arch/mips/cavium/octeonreg.h
103
#define RST_CTL(n) (UINT64_C(0x1180006001640) + (n) * 0x8)
sys/arch/mips/cavium/octeonreg.h
104
#define RST_SOFT_RST UINT64_C(0x1180006001680)
sys/arch/mips/cavium/octeonreg.h
105
#define RST_SOFT_PRST(n) (UINT64_C(0x11800060016c0) + (n) * 0x8)
sys/arch/mips/cavium/octeonreg.h
106
#define RST_PP_POWER UINT64_C(0x1180006001700)
sys/arch/mips/cavium/octeonreg.h
107
#define RST_POWER_DBG UINT64_C(0x1180006001708)
sys/arch/mips/cavium/octeonreg.h
108
#define RST_REF_CNTR UINT64_C(0x1180006001758)
sys/arch/mips/cavium/octeonreg.h
109
#define RST_COLD_DATA(n) (UINT64_C(0x11800060017c0) + (n) * 0x8)
sys/arch/mips/cavium/octeonreg.h
41
#define OCTEON_CVMSEG_LM UINT64_C(0xffffffffffff8000)
sys/arch/mips/cavium/octeonreg.h
42
#define OCTEON_CVMSEG_IO UINT64_C(0xffffffffffffa000)
sys/arch/mips/cavium/octeonreg.h
44
#define OCTEON_IOBDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa200)
sys/arch/mips/cavium/octeonreg.h
45
#define OCTEON_IOBDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb200)
sys/arch/mips/cavium/octeonreg.h
46
#define OCTEON_LMTDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa400)
sys/arch/mips/cavium/octeonreg.h
47
#define OCTEON_LMTDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb400)
sys/arch/mips/cavium/octeonreg.h
86
#define MIO_RST_BOOT UINT64_C(0x1180000001600)
sys/arch/mips/cavium/octeonreg.h
92
#define MIO_FUS_PDF UINT64_C(0x1180000001428)
sys/arch/mips/cavium/octeonreg.h
95
#define RST_BOOT UINT64_C(0x1180006001600)
sys/arch/mips/cavium/octeonreg.h
98
#define RST_DELAY UINT64_C(0x1180006001608)
sys/arch/mips/cavium/octeonreg.h
99
#define RST_CFG UINT64_C(0x1180006001610)
sys/arch/mips/cavium/octeonvar.h
277
#define OCTEON_CCA_NONE UINT64_C(0)
sys/dev/pci/auich.c
1690
actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us;
sys/dev/pci/vio9p.c
64
#define VIO9P_F_MOUNT_TAG (UINT64_C(1) << 0) /* mount tag specified */
sys/net/bpfjit.c
138
#define MAX_ABC_LENGTH (UINT32_MAX + UINT64_C(4)) /* max. width is 4 */
sys/net/npf/npf_portmap.c
222
m = (x >> 4) ^ (UINT64_C(0x1001001001001) * bit);
sys/net/npf/npf_portmap.c
223
r = (m - UINT64_C(0x1001001001001)) & (~m & UINT64_C(0x800800800800800));
sys/net/npf/npf_portmap.c
305
b = UINT64_C(1) << (chunk_bit & PORTMAP_L1_MASK);
sys/net/npf/npf_portmap.c
356
bm1->bits1[off] |= UINT64_C(1) << (v & PORTMAP_L1_MASK);
sys/net/npf/npf_portmap.c
377
b = UINT64_C(1) << (chunk_bit & PORTMAP_L1_MASK);
sys/net/npf/npf_portmap.c
417
b = UINT64_C(1) << (chunk_bit & PORTMAP_L1_MASK);
sys/net/npf/npf_portmap.c
493
bm->bits0[i] = UINT64_C(0);
sys/net/npf/npf_portmap.c
82
#define PORTMAP_L1_TAG (UINT64_C(1)) // use level 1
usr.sbin/npf/npfctl/npf_show.c
423
ctx->seen_marks |= UINT64_C(1) << m;
usr.sbin/npf/npfctl/npf_show.c
484
.negbm = UINT64_C(1) << BM_SRC_NEG,
usr.sbin/npf/npfctl/npf_show.c
490
.negbm = UINT64_C(1) << BM_DST_NEG,
usr.sbin/npf/npfctl/npf_show.c
531
.negbm = UINT64_C(1) << BM_SRC_ENEG,
usr.sbin/npf/npfctl/npf_show.c
536
.negbm = UINT64_C(1) << BM_DST_ENEG,
