TX_DESC_COUNT
for (i = 0; i < TX_DESC_COUNT; i++)
sc->tx.queued = TX_DESC_COUNT;
for (i = 0; i < TX_DESC_COUNT; i++) {
struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT];
if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) {
start, sc->tx.cur, TX_DESC_COUNT,
#define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT)
#define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
#define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT);
i, i + 1, TX_DESC_COUNT,
i, i + 1, TX_DESC_COUNT,
if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs;
__SHIFTIN(TX_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) |
TX_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
for (i=0; i<TX_DESC_COUNT; ++i)
#define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT)
i = sc->sc_tx.cidx % TX_DESC_COUNT;
index = sc->sc_tx.pidx % TX_DESC_COUNT;
if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
for (i = 0; i < TX_DESC_COUNT; i++) {
sc->sc_tx.next, sc->sc_tx.cur, TX_DESC_COUNT,
KASSERT(sc->sc_tx.queued <= TX_DESC_COUNT);
if (sc->sc_tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) {
start, sc->sc_tx.cur, TX_DESC_COUNT,
sc->sc_tx.queued = TX_DESC_COUNT;
for (i = 0; i < TX_DESC_COUNT; i++) {
if (sc->sc_tx.queued >= TX_DESC_COUNT - 1)
nospace = sc->sc_tx.queued >= TX_DESC_COUNT - nsegs;
WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);
sc->sc_tx.desc_ring_paddr, TX_DESC_COUNT);
#define TX_DESC_SIZE (TX_DESC_COUNT * DESC_ALIGN)
#define TX_SKIP(n, o) (((n) + (o)) % TX_DESC_COUNT)