sys/arch/hpcmips/tx/tx39spi.c

138

return tx_conf_read(sc->sc_tc, TX39_SPICTRL_REG) & (TX39_SPICTRL_EMPTY);

sys/arch/hpcmips/tx/tx39spi.c

169

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

174

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

181

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

182

tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_DELAYVAL_SET(reg, n));

sys/arch/hpcmips/tx/tx39spi.c

189

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

190

tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_BAUDRATE_SET(reg, n));

sys/arch/hpcmips/tx/tx39spi.c

197

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

202

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

209

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

214

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

221

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

226

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

233

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

238

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

76

reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

78

tx_conf_write(tc, TX39_SPICTRL_REG, reg);