Symbol: TESR_TCST5
sys/arch/evbmips/ingenic/clock.c
106
writereg(JZ_TC_TESR, TESR_TCST5); /* enable timer 5 */
sys/arch/evbmips/ingenic/clock.c
99
writereg(JZ_TC_TECR, TESR_TCST5); /* disable timer 5 */