TCON_WRITE
TCON_WRITE(sc, TCON_GCTL_REG, val);
TCON_WRITE(sc, TCON0_IO_TRI_REG, 0);
TCON_WRITE(sc, TCON_GCTL_REG, val);
TCON_WRITE(sc, TCON1_IO_POL_REG, 0);
TCON_WRITE(sc, TCON1_IO_TRI_REG, 0xffffffff);
TCON_WRITE(sc, TCON0_CTL_REG, val);
TCON_WRITE(sc, TCON0_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
TCON_WRITE(sc, TCON0_BASIC1_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1));
TCON_WRITE(sc, TCON0_BASIC2_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1));
TCON_WRITE(sc, TCON0_BASIC3_REG, ((hspw - 1) << 16) | (vspw - 1));
TCON_WRITE(sc, TCON0_IO_POL_REG, val);
TCON_WRITE(sc, TCON1_CTL_REG, val);
TCON_WRITE(sc, TCON1_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
TCON_WRITE(sc, TCON1_BASIC1_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
TCON_WRITE(sc, TCON1_BASIC2_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
TCON_WRITE(sc, TCON1_BASIC3_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1));
TCON_WRITE(sc, TCON1_BASIC4_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1));
TCON_WRITE(sc, TCON1_BASIC5_REG, ((hspw - 1) << 16) | (vspw - 1));
TCON_WRITE(sc, TCON_GINT1_REG,
TCON_WRITE(sc, TCON_GINT0_REG, TCON_GINT0_TCON0_VB_INT_EN);
TCON_WRITE(sc, TCON_GINT0_REG, TCON_GINT0_TCON1_VB_INT_EN);
TCON_WRITE(sc, TCON_GINT0_REG, 0);
TCON_WRITE(sc, TCON_GINT0_REG, val & ~status_mask);
TCON_WRITE(sc, SUNXI_TCON_GINT0_REG, 0);
TCON_WRITE(sc, SUNXI_TCON_GINT1_REG,
TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, 0xf0000000);
TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, 0x0);
TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, 0);
TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff);
TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, 0);
TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, 0);
TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_BASIC0_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_BASIC1_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_BASIC2_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_BASIC3_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_IO_POL_REG, lcd_io_cfg0);
TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0);
TCON_WRITE(sc, SUNXI_TCON_GINT1_REG,
TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, val);
TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val);
TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val);
TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val);
TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val);
TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0);
TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff);
TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val);
TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0x0cffffff);
TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0);
TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff);
TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val);
TCON_WRITE(sc, SUNXI_TCON1_BASIC0_REG,
TCON_WRITE(sc, SUNXI_TCON1_BASIC1_REG,
TCON_WRITE(sc, SUNXI_TCON1_BASIC2_REG,
TCON_WRITE(sc, SUNXI_TCON1_BASIC3_REG,
TCON_WRITE(sc, SUNXI_TCON1_BASIC4_REG,
TCON_WRITE(sc, SUNXI_TCON1_BASIC5_REG,
TCON_WRITE(sc, SUNXI_TCON1_IO_POL_REG, val);
TCON_WRITE(sc, SUNXI_TCON_GINT1_REG,
TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val);