BIC
else if (optlist->co_trueop == BIC)
else if (optlist->co_falseop == BIC)
{ "nocache", IGN, BIC, CPU_CONTROL_IDC_ENABLE },
{ "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "cpu.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm6.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm6.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm6.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm6.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm8.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm8.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm8.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "arm8.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm9.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm10.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm11.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm11.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm11.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "arm11.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "armv7.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "armv7.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "armv7.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa110.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa110.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sa110.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sa110.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa11x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa11x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sa11x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sa11x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "ixp12x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "ixp12x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "ixp12x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "ixp12x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "xscale.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "xscale.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "xscale.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "xscale.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sheeva.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sheeva.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sheeva.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sheeva.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },