SUNXI_I2S_CLK_RATE
error = clk_set_rate(sc->sc_clk, SUNXI_I2S_CLK_RATE);
"couldn't set mod clock rate to %u Hz: %d\n", SUNXI_I2S_CLK_RATE, error);
const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : SUNXI_I2S_CLK_RATE;
const u_int mclk_div = SUNXI_I2S_CLK_RATE / rate;