SUNXI_CCU_DIV_GATE
SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents,
SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents,
SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents,
SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents,
SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents,
SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents,
SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents,
SUNXI_CCU_DIV_GATE(H6_CLK_PCIE_MAXI, "pcie_maxi", pll_periph0_parent,
SUNXI_CCU_DIV_GATE(H6_CLK_PCIE_AUX, "pcie_aux", hosc_parent,
SUNXI_CCU_DIV_GATE(H3_CLK_THS, "ths", ths_parents,
SUNXI_CCU_DIV_GATE(H3_CLK_DE, "de", de_parents,
SUNXI_CCU_DIV_GATE(H3_CLK_HDMI, "hdmi", hdmi_parents,
SUNXI_CCU_DIV_GATE(H3_CLK_TCON0, "tcon0", tcon0_parents,
SUNXI_CCU_DIV_GATE(V3S_CLK_TCON, "tcon", tcon_parents,
SUNXI_CCU_DIV_GATE(_id, _name, _parents, _reg, _div, \