SUNXI_CCU_DIV
SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents,
SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents,
SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents,
SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents,
.type = SUNXI_CCU_DIV,
.type = SUNXI_CCU_DIV,
.type = SUNXI_CCU_DIV,
.type = SUNXI_CCU_DIV,
SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(A64_R_CLK_APB0, "apb0", apb0_parents,
SUNXI_CCU_DIV(H6_R_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents,
SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents,
SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents,
SUNXI_CCU_DIV(A31_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(A83T_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(H3_R_CLK_APB0, "apb0", apb0_parents,
SUNXI_CCU_DIV(V3S_CLK_APB1, "apb1", apb1_parents,
SUNXI_CCU_DIV(A80_CLK_GTBUS, "gtbus", gtbus_parents,
SUNXI_CCU_DIV(A80_CLK_AHB0, "ahb0", ahb0_parents,
SUNXI_CCU_DIV(A80_CLK_AHB1, "ahb1", ahb1_parents,
SUNXI_CCU_DIV(A80_CLK_AHB2, "ahb2", ahb2_parents,
SUNXI_CCU_DIV(A80_CLK_APB0, "apb0", apb_parents,
case SUNXI_CCU_DIV: type = "div"; break;
.type = SUNXI_CCU_DIV, \
KASSERT(clk->type == SUNXI_CCU_DIV);
KASSERT(clk->type == SUNXI_CCU_DIV);
KASSERT(clk->type == SUNXI_CCU_DIV);
KASSERT(clk->type == SUNXI_CCU_DIV);
KASSERT(clk->type == SUNXI_CCU_DIV);
SUNXI_CCU_DIV(DE2_CLK_MIXER0_DIV, "mixer0-div", mod_parents,
SUNXI_CCU_DIV(DE2_CLK_MIXER1_DIV, "mixer1-div", mod_parents,
SUNXI_CCU_DIV(DE2_CLK_WB_DIV, "wb-div", mod_parents,