SR_TX_RDY
while (sc->sc_chbase[CH_SR] & SR_TX_RDY) {
while ((ch_base[CH_SR] & SR_TX_RDY) == 0)
while ((ch_base[CH_SR] & SR_TX_RDY) == 0)
while ((vxtregs[CH_SR] & SR_TX_RDY) == 0)
if (((stat[0] & SR_TX_RDY) == 0)
if (((stat[1] & SR_TX_RDY) == 0)