SR18
{IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18,0,5},{SR18,7,7}}},
uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6);
uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6);
{VIASR, SR18, 0xFF, 0x4E},
{VIASR,SR18,0xFF,0x4E},
{VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
{VIASR, SR18, 0xFF, 0x4E},
{VIASR,SR18,0xFF,0x4E},