SR16
{IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16,0,5},{SR16,7,7}}},
uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
{VIASR, SR16, 0xBF, 0x08},
{VIASR,SR16,0xBF,0x08},
{VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
{VIASR, SR16, 0xBF, 0x08},
{VIASR,SR16,0xBF,0x08},