Symbol: SH_
sys/arch/evbsh3/evbsh3/machdep.c
378
_reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
443
_reg_write_2(SH_(PCR), BSC_PCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
453
_reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
460
_reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
464
_reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
468
_reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
475
_reg_write_2(SH_(FRQCR), FRQCR_VAL);
sys/arch/evbsh3/evbsh3/machdep.c
482
_reg_write_4(SH_(CCR), 0x1);
sys/arch/hpc/stand/hpcboot/sh3/sh_arch.h
113
SH_(7709);
sys/arch/hpc/stand/hpcboot/sh3/sh_arch.h
114
SH_(7709A);
sys/arch/hpc/stand/hpcboot/sh3/sh_arch.h
115
SH_(7707);
sys/arch/mmeye/mmeye/machdep.c
472
_reg_write_2(SH_(RTCSR), 0xa594);
sys/arch/mmeye/mmeye/machdep.c
478
_reg_write_2(SH_(RTCNT), 0xa500);
sys/arch/mmeye/mmeye/machdep.c
492
_reg_write_2(SH_(RFCR), 0xa400);
sys/arch/mmeye/mmeye/machdep.c
655
evtcode = _reg_read_4(SH_(INTEVT));
sys/arch/mmeye/stand/boot/clock.c
40
_reg_write_1(SH_(TOCR), TOCR_TCOE);
sys/arch/mmeye/stand/boot/clock.c
41
_reg_write_2(SH_(TCR0), TCR_TPSC_P4);
sys/arch/mmeye/stand/boot/clock.c
42
_reg_bset_1(SH_(TSTR), TSTR_STR0);
sys/arch/mmeye/stand/boot/clock.c
51
t1 = _reg_read_4(SH_(TCNT0));
sys/arch/mmeye/stand/boot/clock.c
53
t2 = _reg_read_4(SH_(TCNT0));
sys/arch/sh3/dev/rtc.c
115
_reg_write_1(SH_(RCR1), 0);
sys/arch/sh3/dev/rtc.c
118
_reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
sys/arch/sh3/dev/rtc.c
159
_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);
sys/arch/sh3/dev/rtc.c
162
uint8_t r = _reg_read_1(SH_(RCR1));
sys/arch/sh3/dev/rtc.c
165
_reg_write_1(SH_(RCR1), r);
sys/arch/sh3/dev/rtc.c
175
dt->dt_ ## x = bcdtobin(_reg_read_1(SH_(R ## y ## CNT)))
sys/arch/sh3/dev/rtc.c
184
} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);
sys/arch/sh3/dev/rtc.c
224
r = _reg_read_1(SH_(RCR2));
sys/arch/sh3/dev/rtc.c
227
_reg_write_1(SH_(RCR2), (r & ~SH_RCR2_START) | SH_RCR2_RESET);
sys/arch/sh3/dev/rtc.c
236
_reg_write_1(SH_(R ## x ## CNT), bintobcd(dt->dt_ ## y))
sys/arch/sh3/dev/rtc.c
248
_reg_write_1(SH_(RCR2), r);
sys/arch/sh3/dev/rtc.c
98
r = _reg_read_1(SH_(RCR2));
sys/arch/sh3/sh3/clock.c
103
_reg_bclr_1(SH_(TSTR), TSTR_STR##x); \
sys/arch/sh3/sh3/clock.c
104
_reg_write_4(SH_(TCNT ## x), 0xffffffff); \
sys/arch/sh3/sh3/clock.c
105
_reg_bset_1(SH_(TSTR), TSTR_STR##x); \
sys/arch/sh3/sh3/clock.c
109
(0xffffffff - _reg_read_4(SH_(TCNT ## x)))
sys/arch/sh3/sh3/clock.c
119
_reg_write_2(SH_(TCR0), 0);
sys/arch/sh3/sh3/clock.c
120
_reg_write_2(SH_(TCR1), 0);
sys/arch/sh3/sh3/clock.c
121
_reg_write_2(SH_(TCR2), 0);
sys/arch/sh3/sh3/clock.c
124
_reg_write_1(SH_(RCR1), 0);
sys/arch/sh3/sh3/clock.c
127
_reg_write_1(SH_(TSTR), 0);
sys/arch/sh3/sh3/clock.c
134
_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
sys/arch/sh3/sh3/clock.c
138
_reg_write_2(SH_(TCR0),
sys/arch/sh3/sh3/clock.c
143
_reg_bset_1(SH_(RCR2), SH_RCR2_ENABLE);
sys/arch/sh3/sh3/clock.c
168
_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
sys/arch/sh3/sh3/clock.c
183
_reg_write_1(SH_(TSTR), 0);
sys/arch/sh3/sh3/clock.c
213
return 0xffffffff - _reg_read_4(SH_(TCNT2));
sys/arch/sh3/sh3/clock.c
243
_reg_bclr_1(SH_(TSTR), TSTR_STR0);
sys/arch/sh3/sh3/clock.c
247
_reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16);
sys/arch/sh3/sh3/clock.c
250
_reg_write_2(SH_(TCR0), TCR_UNIE |
sys/arch/sh3/sh3/clock.c
255
_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
sys/arch/sh3/sh3/clock.c
256
_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
sys/arch/sh3/sh3/clock.c
262
_reg_bset_1(SH_(TSTR), TSTR_STR0);
sys/arch/sh3/sh3/clock.c
267
_reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4);
sys/arch/sh3/sh3/clock.c
268
_reg_write_4(SH_(TCOR1), 0xffffffff);
sys/arch/sh3/sh3/clock.c
273
_reg_write_2(SH_(TCR2), TCR_TPSC_P4);
sys/arch/sh3/sh3/clock.c
274
_reg_write_4(SH_(TCOR2), 0xffffffff);
sys/arch/sh3/sh3/clock.c
279
_reg_bset_1(SH_(TSTR), TSTR_STR2);
sys/arch/sh3/sh3/exception.c
158
trapcode = _reg_read_4(SH_(TRA)) >> 2;
sys/arch/sh3/sh3/interrupt.c
391
printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));
sys/arch/sh3/sh3/mmu.c
111
_reg_write_4(SH_(PTEH), asid);
sys/arch/sh3/sh3/sh3_machdep.c
195
_reg_write_2(SH_(BBRA), 0); /* disable channel A */
sys/arch/sh3/sh3/sh3_machdep.c
196
_reg_write_2(SH_(BBRB), 0); /* disable channel B */
sys/arch/sh3/sh3/sh3_machdep.c
558
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);