BECC_CSR_WRITE
BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK);
BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK);
BECC_CSR_WRITE(BECC_PSTR2,
BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */);
BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */);
BECC_CSR_WRITE(BECC_POMR3,
BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate);
BECC_CSR_WRITE(BECC_POCR, 0);
BECC_CSR_WRITE(BECC_ICSTR, intr_steer & ICU_VALID_MASK);
BECC_CSR_WRITE(BECC_ICMR, ~intr_enabled & ICU_VALID_MASK);
BECC_CSR_WRITE(BECC_POCR, 0);
BECC_CSR_WRITE(BECC_PMISR, reg & 0x000f000d);
BECC_CSR_WRITE(BECC_PSISR, reg & 0x000f0210);
BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF);
BECC_CSR_WRITE(BECC_TSCRB, TSCRx_TIF);
BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1);
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM);
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF);
BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1);
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM);
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM | TSCRx_TIF);