sys/arch/arm/rockchip/rk3399_pcie.c

49

#define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0)

sys/arch/arm/rockchip/rk3399_pcie.c

50

#define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1)

sys/arch/arm/rockchip/rk3399_pcie.c

52

#define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0)

sys/arch/arm/rockchip/rk3399_pcie.c

53

#define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1)

sys/arch/arm/rockchip/rk3399_pcie.c

55

#define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */

sys/arch/arm/rockchip/rk3399_pcie.c

56

#define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */

sys/arch/arm/rockchip/rk3399_pcie.c

57

#define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1)

sys/arch/arm/rockchip/rk3399_pcie.c

58

#define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1)

sys/arch/arm/rockchip/rk3399_pcie.c

59

#define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */

sys/arch/arm/rockchip/rk3399_pcie.c

70

#define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1)

sys/arch/arm/rockchip/rk3399_pcie.c

71

#define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0)