sys/arch/arm/nvidia/tegra210_xusbpad.c

236

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

239

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_5_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

242

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

244

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

246

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

249

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

252

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

255

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

258

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

261

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

264

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

267

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

269

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

274

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

278

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

291

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

305

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

319

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

321

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

334

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

347

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

352

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

354

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

356

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

369

SETCLR4(sc, XUSB_PADCTL_USB3_PAD_MUX_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

385

SETCLR4(sc, XUSB_PADCTL_USB2_PAD_MUX_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

390

SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

395

SETCLR4(sc, XUSB_PADCTL_USB2_OTG_PADn_CTL_0_REG(index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

401

SETCLR4(sc, XUSB_PADCTL_USB2_OTG_PADn_CTL_1_REG(index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

409

SETCLR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_REG(index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

413

SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

418

SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

421

SETCLR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

434

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

437

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

440

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

442

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

444

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

447

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

450

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

453

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

456

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

459

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

462

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

465

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

467

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

472

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

476

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

489

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

503

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

517

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

519

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

532

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

545

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

550

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

552

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

554

SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

568

SETCLR4(sc, XUSB_PADCTL_USB3_PAD_MUX_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

712

SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

849

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

850

SETCLR4(sc, port->reg, __SHIFTIN(modeval, port->mask), port->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

869

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

870

SETCLR4(sc, port->reg, __SHIFTIN(companion, port->mask), port->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

872

SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_1_REG(port->index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

875

SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_REG(port->index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

879

SETCLR4(sc, XUSB_PADCTL_UPHY_USB3_PADn_ECTL_4_REG(port->index),

sys/arch/arm/nvidia/tegra210_xusbpad.c

884

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

887

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

890

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

893

SETCLR4(sc, XUSB_PADCTL_VBUS_OC_MAP_REG,

sys/arch/arm/nvidia/tegra210_xusbpad.c

937

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN);

sys/arch/arm/nvidia/tegra210_xusbpad.c

939

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_CLAMP_EN_EARLY);

sys/arch/arm/nvidia/tegra210_xusbpad.c

941

SETCLR4(sc, XUSB_PADCTL_ELPG_PROGRAM_1_REG, 0, XUSB_PADCTL_ELPG_PROGRAM_1_AUX_MUX_LP0_VCORE_DOWN);