SET32
SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
SET32(sc, RADEON_CRTC_EXT_CNTL,
SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN);
SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN);
SET32(sc, reg, mask);
SET32(sc, fpreg, fpval);
SET32(sc, RADEON_DAC_CNTL2,
SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL);
SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT,
SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE |
SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE);
SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
SET32(dp->rd_softc, gencntl, bit);
SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK);
SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK);
SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK);
SET32(sc, RADEON_DAC_CNTL2,
SET32(sc, RADEON_FP_GEN_CNTL,
SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
SET32(sc, ric->ric_register, RADEON_GPIO_SW_USE);
SET32(sc, ric->ric_register, RADEON_GPIO_EN_1);
SET32(sc, ric->ric_register, RADEON_GPIO_SW_DONE);