SDHC_READ
const uint32_t old = SDHC_READ(sc, reg);
ista = SDHC_READ(sc, SD_ISTA_REG);
const u_int clkc = SDHC_READ(sc, SD_CLKC_REG);
clkc = SDHC_READ(sc, SD_CLKC_REG);
clk2 = SDHC_READ(sc, SD_CLK2_REG);
const uint32_t stat = SDHC_READ(sc, SD_STAT_REG);
const uint32_t esta = SDHC_READ(sc, SD_ESTA_REG);
SDHC_READ(sc, SD_CLKC_REG) & ~SD_CLKC_MEM_PWR);
enhc = SDHC_READ(sc, SD_ENHC_REG);
cntl = SDHC_READ(sc, SD_CNTL_REG);
cntl = SDHC_READ(sc, SD_CNTL_REG);
pdma = SDHC_READ(sc, SD_PDMA_REG);
pdma = SDHC_READ(sc, SD_PDMA_REG);
cmd->c_resp[i - 1] = SDHC_READ(sc, SD_ARGU_REG);
cmd->c_resp[0] = SDHC_READ(sc, SD_ARGU_REG);
srst = SDHC_READ(sc, SD_SRST_REG);
const uint32_t clkc = SDHC_READ(sc, SD_CLKC_REG);
SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_1_8V);
SDHC_READ(sc, SDHC_CAPABILITIES) | SDHC_VOLTAGE_SUPP_3_0V);
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
if (SDHC_READ(sc, SDHC_CLOCK_CTL) & SDHC_INTCLK_STABLE)
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
hctl = SDHC_READ(hmsc, SDHC_HOST_CTL);