Symbol: BCM53XXX_IRQ
sys/arch/arm/broadcom/bcm53xx_intr.h
100
#define IRQ_DS_3_PINS_BUS BCM53XXX_IRQ(76, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
101
#define IRQ_DS_4_PINS_BUS BCM53XXX_IRQ(77, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
102
#define IRQ_DDR_CONTROLLER BCM53XXX_IRQ(78, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
103
#define IRQ_DMAC BCM53XXX_IRQ(79, 6) /* 16 */
sys/arch/arm/broadcom/bcm53xx_intr.h
104
#define IRQ_DMAC_ABORT BCM53XXX_IRQ(95, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
105
#define IRQ_NAND_RD_MISS BCM53XXX_IRQ(96, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
106
#define IRQ_NAND_BLK_ERASE_COMP BCM53XXX_IRQ(97, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
107
#define IRQ_NAND_COPY_BACK_COMP BCM53XXX_IRQ(98, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
108
#define IRQ_NAND_PGM_PAGE_COMP BCM53XXX_IRQ(99, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
109
#define IRQ_NAND_RO_CTLR_READY BCM53XXX_IRQ(100, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
110
#define IRQ_NAND_RB_B BCM53XXX_IRQ(101, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
111
#define IRQ_NAND_ECC_MIPS_UNCORR BCM53XXX_IRQ(102, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
112
#define IRQ_NAND_ECC_MIPS_CORR BCM53XXX_IRQ(103, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
114
#define IRQ_SPI_FULLNESS_REACHED BCM53XXX_IRQ(104, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
115
#define IRQ_SPI_TRUNCATED BCM53XXX_IRQ(105, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
116
#define IRQ_SPI_IMPATIENT BCM53XXX_IRQ(106, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
117
#define IRQ_SPI_SESSION_DONE BCM53XXX_IRQ(107, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
118
#define IRQ_SPI_INTERRUPT_OVERREAD BCM53XXX_IRQ(108, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
119
#define IRQ_SPI_MSPI_INTERRUPT_DONE BCM53XXX_IRQ(109, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
121
BCM53XXX_IRQ(110, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
122
#define IRQ_USB2 BCM53XXX_IRQ(111, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
124
#define IRQ_CCA BCM53XXX_IRQ(117, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
125
#define IRQ_UART2 BCM53XXX_IRQ(118, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
126
#define IRQ_GPIO BCM53XXX_IRQ(119, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
127
#define IRQ_I2S BCM53XXX_IRQ(120, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
128
#define IRQ_SMBUS1 BCM53XXX_IRQ(121, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
129
#define IRQ_TIMER0_1 BCM53XXX_IRQ(122, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
130
#define IRQ_TIMER0_2 BCM53XXX_IRQ(123, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
131
#define IRQ_TIMER1_1 BCM53XXX_IRQ(124, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
132
#define IRQ_TIMER1_2 BCM53XXX_IRQ(125, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
133
#define IRQ_RNG BCM53XXX_IRQ(126, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
134
#define IRQ_SWITCH_SOC BCM53XXX_IRQ(127, 7) /* 32 */
sys/arch/arm/broadcom/bcm53xx_intr.h
135
#define IRQ_NETWORK_LINK_EVENT BCM53XXX_IRQ(127, 7) /* 8 */
sys/arch/arm/broadcom/bcm53xx_intr.h
136
#define IRQ_PHY BCM53XXX_IRQ(135, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
137
#define IRQ_TIMESYNC BCM53XXX_IRQ(136, 7)
sys/arch/arm/broadcom/bcm53xx_intr.h
138
#define IRQ_IMP_SLEEP_TIMER BCM53XXX_IRQ(137, 7) /* 3 */
sys/arch/arm/broadcom/bcm53xx_intr.h
139
#define IRQ_PCIE_INT0 BCM53XXX_IRQ(159, 55) /* 6 */
sys/arch/arm/broadcom/bcm53xx_intr.h
140
#define IRQ_PCIE_INT1 BCM53XXX_IRQ(165, 55) /* 6 */
sys/arch/arm/broadcom/bcm53xx_intr.h
141
#define IRQ_PCIE_INT2 BCM53XXX_IRQ(171, 55) /* 6 */
sys/arch/arm/broadcom/bcm53xx_intr.h
142
#define IRQ_SDIO BCM53XXX_IRQ(177, 55)
sys/arch/arm/broadcom/bcm53xx_intr.h
143
#define IRQ_GMAC0 BCM53XXX_IRQ(179, 55)
sys/arch/arm/broadcom/bcm53xx_intr.h
144
#define IRQ_GMAC1 BCM53XXX_IRQ(180, 55)
sys/arch/arm/broadcom/bcm53xx_intr.h
97
#define IRQ_DS_0_PINS_BUS BCM53XXX_IRQ(73, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
98
#define IRQ_DS_1_PINS_BUS BCM53XXX_IRQ(74, 6)
sys/arch/arm/broadcom/bcm53xx_intr.h
99
#define IRQ_DS_2_PINS_BUS BCM53XXX_IRQ(75, 6)