sys/arch/evbsh3/t_sh7706lan/scimci.c

251

while ((SHREG_SCSSR & SCSSR_TDRE) == 0)

sys/arch/evbsh3/t_sh7706lan/scimci.c

627

while ((SHREG_SCSSR & SCSSR_TDRE) == 0)

sys/arch/hpc/stand/hpcboot/sh3/dev/sh.h

224

while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0)

sys/arch/hpc/stand/hpcboot/sh3/dev/sh.h

231

_reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \

sys/arch/sh3/dev/sci.c

1231

if ((SHREG_SCSSR & SCSSR_TDRE) != 0) {

sys/arch/sh3/dev/sci.c

311

SHREG_SCSSR &= SCSSR_TDRE; /* Clear Status */

sys/arch/sh3/dev/sci.c

328

while ((SHREG_SCSSR & SCSSR_TDRE) == 0)

sys/arch/sh3/dev/sci.c

335

SHREG_SCSSR &= ~SCSSR_TDRE;

sys/arch/sh3/dev/sci.c

845

SHREG_SCSSR &= ~SCSSR_TDRE;

sys/arch/sh3/dev/sci.c

847

SHREG_SCSSR |= SCSSR_TDRE;