SCN_REG
#define CH_MR SCN_REG(0) /* rw mode register */
#define CH_SR SCN_REG(1) /* ro status register */
#define CH_CSR SCN_REG(1) /* wo clock select reg */
#define CH_CR SCN_REG(2) /* wo command reg */
#define CH_DAT SCN_REG(3) /* rw data reg */
#define DU_IPCR SCN_REG(4) /* ro input port change reg */
#define DU_ACR SCN_REG(4) /* wo aux control reg */
#define DU_ISR SCN_REG(5) /* ro interrupt stat reg */
#define DU_IMR SCN_REG(5) /* wo interrupt mask reg */
#define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */
#define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */
#define DU_IP SCN_REG(13) /* ro input port */
#define DU_OPCR SCN_REG(13) /* wo output port cfg reg */
#define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */
#define DU_OPSET SCN_REG(14) /* wo output port set */
#define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */
#define DU_OPCLR SCN_REG(15) /* wo output port reset */
#define CH_MR(x) SCN_REG(0 + 8*(x)) /* rw mode register */
#define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */
#define CH_CSR(x) SCN_REG(1 + 8*(x)) /* wo clock select reg */
#define CH_CR(x) SCN_REG(2 + 8*(x)) /* wo command reg */
#define CH_DAT(x) SCN_REG(3 + 8*(x)) /* rw data reg */
#define DU_IPCR SCN_REG(4) /* ro input port change reg */
#define DU_ACR SCN_REG(4) /* wo aux control reg */
#define DU_ISR SCN_REG(5) /* ro interrupt stat reg */
#define DU_IMR SCN_REG(5) /* wo interrupt mask reg */
#define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */
#define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */
#define DU_IP SCN_REG(13) /* ro input port */
#define DU_OPCR SCN_REG(13) /* wo output port cfg reg */
#define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */
#define DU_OPSET SCN_REG(14) /* wo output port set */
#define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */
#define DU_OPCLR SCN_REG(15) /* wo output port reset */
#define QVA_FIRSTREG SCN_REG(0)
#define QVA_WINSIZE (SCN_REG(16) - SCN_REG(0))