Symbol: SBIC_CSR_MIS_2
sys/arch/acorn32/podulebus/sbic.c
1345
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/arch/acorn32/podulebus/sbic.c
1369
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
sys/arch/acorn32/podulebus/sbic.c
1370
case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
sys/arch/acorn32/podulebus/sbic.c
1393
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2043
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2054
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2079
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2080
case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2144
case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2157
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
sys/arch/acorn32/podulebus/sbic.c
2225
(csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE))) {
sys/arch/acorn32/podulebus/sbic.c
978
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
sys/arch/acorn32/podulebus/sbic.c
979
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
sys/arch/acorn32/podulebus/sbic.c
988
if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) {
sys/arch/acorn32/podulebus/sbic.c
997
} else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
sys/arch/amiga/dev/sbic.c
1042
} while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE)
sys/arch/amiga/dev/sbic.c
1043
&& csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO);
sys/arch/amiga/dev/sbic.c
1051
if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) {
sys/arch/amiga/dev/sbic.c
1060
} else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) {
sys/arch/amiga/dev/sbic.c
1410
case SBIC_CSR_MIS_2|CMD_PHASE:
sys/arch/amiga/dev/sbic.c
1433
case SBIC_CSR_MIS_2|DATA_OUT_PHASE:
sys/arch/amiga/dev/sbic.c
1434
case SBIC_CSR_MIS_2|DATA_IN_PHASE:
sys/arch/amiga/dev/sbic.c
1463
case SBIC_CSR_MIS_2|STATUS_PHASE:
sys/arch/amiga/dev/sbic.c
2217
case SBIC_CSR_MIS_2|CMD_PHASE:
sys/arch/amiga/dev/sbic.c
2228
case SBIC_CSR_MIS_2|STATUS_PHASE:
sys/arch/amiga/dev/sbic.c
2281
case SBIC_CSR_MIS_2|DATA_OUT_PHASE:
sys/arch/amiga/dev/sbic.c
2282
case SBIC_CSR_MIS_2|DATA_IN_PHASE:
sys/arch/amiga/dev/sbic.c
2351
case SBIC_CSR_MIS_2|MESG_IN_PHASE:
sys/arch/amiga/dev/sbic.c
2363
case SBIC_CSR_MIS_2|MESG_OUT_PHASE:
sys/arch/amiga/dev/sbic.c
2436
csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
sys/arch/mvme68k/dev/sbic.c
1027
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
sys/arch/mvme68k/dev/sbic.c
1028
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
sys/arch/mvme68k/dev/sbic.c
1067
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
sys/arch/mvme68k/dev/sbic.c
1382
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/arch/mvme68k/dev/sbic.c
1392
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/arch/mvme68k/dev/sbic.c
2111
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/arch/mvme68k/dev/sbic.c
2119
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/arch/mvme68k/dev/sbic.c
2157
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
sys/arch/mvme68k/dev/sbic.c
2158
case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
sys/arch/mvme68k/dev/sbic.c
2256
case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
sys/arch/mvme68k/dev/sbic.c
2277
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
sys/arch/mvme68k/dev/sbic.c
2387
csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
sys/arch/sgimips/stand/common/iris_scsi.c
274
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
sys/arch/sgimips/stand/common/iris_scsi.c
275
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
sys/arch/sgimips/stand/common/iris_scsi.c
309
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
sys/arch/sgimips/stand/common/iris_scsi.c
371
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/arch/sgimips/stand/common/iris_scsi.c
381
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/arch/sgimips/stand/common/iris_scsi.c
397
case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
sys/arch/sgimips/stand/common/iris_scsi.c
401
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
sys/arch/sgimips/stand/common/iris_scsi.c
420
case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
sys/arch/sgimips/stand/common/iris_scsi.c
435
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
sys/dev/ic/wd33c93.c
1061
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
sys/dev/ic/wd33c93.c
1062
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
sys/dev/ic/wd33c93.c
1101
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
sys/dev/ic/wd33c93.c
1913
case SBIC_CSR_MIS_2 | CMD_PHASE:
sys/dev/ic/wd33c93.c
1922
case SBIC_CSR_MIS_2 | STATUS_PHASE:
sys/dev/ic/wd33c93.c
1950
case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
sys/dev/ic/wd33c93.c
1954
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
sys/dev/ic/wd33c93.c
2015
case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
sys/dev/ic/wd33c93.c
2036
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
sys/dev/ic/wd33c93.c
2123
csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {