RK_MUX
RK_MUX(RK3288_SCLK_UART0, "sclk_uart0", uart0_parents, CLKSEL_CON(13), __BITS(9,8)),
RK_MUX(RK3288_SCLK_UART1, "sclk_uart1", uart1_parents, CLKSEL_CON(14), __BITS(9,8)),
RK_MUX(RK3288_SCLK_UART2, "sclk_uart2", uart2_parents, CLKSEL_CON(15), __BITS(9,8)),
RK_MUX(RK3288_SCLK_UART3, "sclk_uart3", uart3_parents, CLKSEL_CON(16), __BITS(9,8)),
RK_MUX(RK3288_SCLK_UART4, "sclk_uart4", uart4_parents, CLKSEL_CON(3), __BITS(9,8)),
RK_MUX(0, "uart_src", mux_2plls_parents, CLKSEL_CON(15), __BIT(15)),
RK_MUX(RK3288_SCLK_MAC, "mac_clk", mac_parents, CLKSEL_CON(21), __BIT(4)),
RK_MUX(RK3328_HDMIPHY, "hdmiphy", mux_hdmiphy_parents, MISC_CON, __BIT(13)),
RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, MISC_CON, __BIT(15)),
RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, CLKSEL_CON(14), __BITS(9,8)),
RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, CLKSEL_CON(16), __BITS(9,8)),
RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)),
RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(6), __BITS(9,8)),
RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(8), __BITS(9,8)),
RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(10), __BITS(9,8)),
RK_MUX(0, "clk_spdif_mux", mux_spdif_parents, CLKSEL_CON(10), __BITS(9,8)),
RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)),
RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)),
RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)),
RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)),
RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)),
RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)),
RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)),
RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)),
RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)),
RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)),
RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)),
RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)),
RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)),
RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)),
RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)),
RK_MUX(RK3588_I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout",
RK_MUX(RK3588_CLK_SPDIF0, "clk_spdif0", clk_spdif0_parents,
RK_MUX(RK3588_CLK_SPDIF1, "clk_spdif1", clk_spdif1_parents,
RK_MUX(RK3588_CLK_UART1, "clk_uart1", clk_uart1_parents,
RK_MUX(RK3588_CLK_UART2, "clk_uart2", clk_uart2_parents,
RK_MUX(RK3588_CLK_UART3, "clk_uart3", clk_uart3_parents,
RK_MUX(RK3588_CLK_UART4, "clk_uart4", clk_uart4_parents,
RK_MUX(RK3588_CLK_UART5, "clk_uart5", clk_uart5_parents,
RK_MUX(RK3588_CLK_UART6, "clk_uart6", clk_uart6_parents,
RK_MUX(RK3588_CLK_UART7, "clk_uart7", clk_uart7_parents,
RK_MUX(RK3588_CLK_UART8, "clk_uart8", clk_uart8_parents,
RK_MUX(RK3588_CLK_UART9, "clk_uart9", clk_uart9_parents,
RK_MUX(RK3588_CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx",
RK_MUX(RK3588_CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx",
RK_MUX(RK3588_CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_parents,
RK_MUX(RK3588_CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_parents,
RK_MUX(RK3588_ACLK_VOP_SUB_SRC, "aclk_vop_sub_src",
RK_MUX(RK3588_CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx",
RK_MUX(RK3588_CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx",
RK_MUX(RK3588_CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx",
RK_MUX(RK3588_CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx",
RK_MUX(RK3588_CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx",
RK_MUX(RK3588_CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx",
RK_MUX(RK3588_I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout",
RK_MUX(RK3588_CLK_SPDIF3, "clk_spdif3", clk_spdif3_parents,
RK_MUX(RK3588_CLK_SPDIF4, "clk_spdif4", clk_spdif4_parents,
RK_MUX(RK3588_CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0",
RK_MUX(RK3588_CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1",
RK_MUX(RK3588_CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2",
RK_MUX(RK3588_CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx",
RK_MUX(RK3588_CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx",
RK_MUX(RK3588_I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout",
RK_MUX(RK3588_CLK_UART0, "clk_uart0", clk_uart0_parents,
RK_MUX(RK3588_CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_parents,
RK_MUX(RK3588_I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout",
RK_MUX(RK3588_CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_parents,
RK_MUX(RK3588_I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout",
RK_MUX(RK3588_CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx",
RK_MUX(RK3588_CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx",