RK3588_EMMC_IOC_REG
{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(3,0) },
{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(7,4) },
{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(11,8) },
{ RK3588_EMMC_IOC_REG + 0x0040, __BITS(15,12) },
{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(3,0) },
{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(7,4) },
{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(11,8) },
{ RK3588_EMMC_IOC_REG + 0x0058, __BITS(15,12) },
{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(3,0) },
{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(7,4) },
{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(11,8) },
{ RK3588_EMMC_IOC_REG + 0x005c, __BITS(15,12) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(1,0) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(3,2) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(5,4) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(7,6) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(9,8) },
{ RK3588_EMMC_IOC_REG + 0x0120, __BITS(11,10) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(1,0) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(3,2) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(5,4) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(7,6) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(9,8) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(11,10) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(13,12) },
{ RK3588_EMMC_IOC_REG + 0x012c, __BITS(15,14) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(0) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(1) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(2) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(3) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(4) },
{ RK3588_EMMC_IOC_REG + 0x0220, __BIT(5) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(0) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(1) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(2) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(3) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(4) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(5) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(6) },
{ RK3588_EMMC_IOC_REG + 0x022c, __BIT(7) },