RISC_BLOCK
#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
#define RISC_MTR2100 RISC_BLOCK+0x30
#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
#define TCR RISC_BLOCK+0x46 /* W : Test Control */
#define TMR RISC_BLOCK+0x48 /* W : Test Mode */
case RISC_BLOCK:
pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
case RISC_BLOCK:
sbc->sbus_poff[RISC_BLOCK >> _BLK_REG_SHFT] = SBUS_RISC_REGS_OFF;