REG_WRITE - NetBSD

sys/arch/mips/adm5120/adm5120_intr.c

181

REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK);

sys/arch/mips/adm5120/adm5120_intr.c

219

REG_WRITE(ICU_MODE_REG,

sys/arch/mips/adm5120/adm5120_intr.c

222

REG_WRITE(ICU_MODE_REG,

sys/arch/mips/adm5120/adm5120_intr.c

226

REG_WRITE(ICU_ENABLE_REG, irqmask);

sys/arch/mips/adm5120/adm5120_intr.c

257

REG_WRITE(ICU_DISABLE_REG, irqmask);

sys/arch/mips/adm5120/dev/ahci.c

1248

REG_WRITE(ADMHCD_REG_HOSTHEAD, (uint32_t)ep);

sys/arch/mips/adm5120/dev/ahci.c

1249

REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP | ADMHCD_DMA_EN);

sys/arch/mips/adm5120/dev/ahci.c

1277

REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);

sys/arch/mips/adm5120/dev/ahci.c

291

REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* disable interrupts */

sys/arch/mips/adm5120/dev/ahci.c

292

REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_SW_RESET); /* reset */

sys/arch/mips/adm5120/dev/ahci.c

297

REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_HOST_EN);

sys/arch/mips/adm5120/dev/ahci.c

298

REG_WRITE(ADMHCD_REG_HOSTHEAD, 0x00000000);

sys/arch/mips/adm5120/dev/ahci.c

299

REG_WRITE(ADMHCD_REG_FMINTERVAL, 0x20002edf);

sys/arch/mips/adm5120/dev/ahci.c

300

REG_WRITE(ADMHCD_REG_LSTHRESH, 0x628);

sys/arch/mips/adm5120/dev/ahci.c

301

REG_WRITE(ADMHCD_REG_RHDESCR, ADMHCD_NPS | ADMHCD_LPSC);

sys/arch/mips/adm5120/dev/ahci.c

302

REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);

sys/arch/mips/adm5120/dev/ahci.c

304

REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* XXX: enable interrupts */

sys/arch/mips/adm5120/dev/ahci.c

603

#define WPS(x) REG_WRITE(ADMHCD_REG_PORTSTATUS0+(index-1)*4, (x))

sys/arch/mips/adm5120/dev/ahci.c

694

#define WPS(x) REG_WRITE(ADMHCD_REG_PORTSTATUS0+(index-1)*4, (x))

sys/arch/mips/adm5120/dev/ahci.c

929

REG_WRITE(ADMHCD_REG_HOSTHEAD, (uint32_t)ep);

sys/arch/mips/adm5120/dev/ahci.c

930

REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP | ADMHCD_DMA_EN);

sys/arch/mips/adm5120/dev/ahci.c

963

REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);

sys/arch/mips/adm5120/dev/if_admsw.c

1033

REG_WRITE(CPUP_CONF_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

1037

REG_WRITE(ADMSW_INT_ST, INT_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

1040

REG_WRITE(ADMSW_INT_MASK, REG_READ(ADMSW_INT_MASK) &

sys/arch/mips/adm5120/dev/if_admsw.c

1076

REG_WRITE(CPUP_CONF_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

1082

REG_WRITE(ADMSW_INT_ST, INT_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

1085

REG_WRITE(ADMSW_INT_MASK, INT_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

1136

REG_WRITE(MAC_WT1_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

1141

REG_WRITE(MAC_WT0_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

1168

REG_WRITE(CPUP_CONF_REG, conf);

sys/arch/mips/adm5120/dev/if_admsw.c

1255

REG_WRITE(PHY_CNTL2_REG, new);

sys/arch/mips/adm5120/dev/if_admsw.c

224

REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));

sys/arch/mips/adm5120/dev/if_admsw.c

225

REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));

sys/arch/mips/adm5120/dev/if_admsw.c

226

REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));

sys/arch/mips/adm5120/dev/if_admsw.c

227

REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));

sys/arch/mips/adm5120/dev/if_admsw.c

242

REG_WRITE(VLAN_G1_REG, i);

sys/arch/mips/adm5120/dev/if_admsw.c

244

REG_WRITE(VLAN_G2_REG, i);

sys/arch/mips/adm5120/dev/if_admsw.c

253

REG_WRITE(PORT_CONF0_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

255

REG_WRITE(CPUP_CONF_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

266

REG_WRITE(PHY_CNTL2_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

270

REG_WRITE(ADMSW_SW_RES, 0x1);

sys/arch/mips/adm5120/dev/if_admsw.c

274

REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO);

sys/arch/mips/adm5120/dev/if_admsw.c

277

REG_WRITE(CPUP_CONF_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

281

REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

283

REG_WRITE(PHY_CNTL2_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

287

REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);

sys/arch/mips/adm5120/dev/if_admsw.c

289

REG_WRITE(ADMSW_INT_MASK, INT_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

290

REG_WRITE(ADMSW_INT_ST, INT_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

301

REG_WRITE(FC_TH_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

307

REG_WRITE(MAC_WT1_REG,

sys/arch/mips/adm5120/dev/if_admsw.c

312

REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) |

sys/arch/mips/adm5120/dev/if_admsw.c

320

REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE);

sys/arch/mips/adm5120/dev/if_admsw.c

660

REG_WRITE(SEND_TRIG_REG, 1);

sys/arch/mips/adm5120/dev/if_admsw.c

804

REG_WRITE(ADMSW_INT_ST, pending);

sys/arch/mips/adm5120/dev/uart.c

145

REG_WRITE(UART_CR_REG,UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN);

sys/arch/mips/adm5120/dev/uart.c

340

REG_WRITE(UART_ECR_REG, UART_ECR_RSR);

sys/arch/virt68k/dev/virtctrl.c

79

REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_PANIC);

sys/arch/virt68k/dev/virtctrl.c

81

REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_HALT);

sys/arch/virt68k/dev/virtctrl.c

83

REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_RESET);

sys/dev/goldfish/gfpic.c

69

REG_WRITE(sc, GFPIC_DISABLE_ALL, 0);

sys/dev/goldfish/gfpic.c

82

REG_WRITE(sc, GFPIC_ENABLE, (1U << pirq));

sys/dev/goldfish/gfpic.c

95

REG_WRITE(sc, GFPIC_DISABLE, (1U << pirq));

sys/dev/goldfish/gftty.c

313

REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);

sys/dev/goldfish/gftty.c

346

REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);

sys/dev/goldfish/gftty.c

357

REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);

sys/dev/goldfish/gftty.c

390

REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);

sys/dev/goldfish/gftty.c

471

REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);

sys/dev/goldfish/gftty.c

487

REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);

sys/dev/goldfish/gftty.c

527

REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);

sys/dev/goldfish/gftty.c

653

REG_WRITE(sc, GFTTY_CMD, CMD_WRITE_BUFFER);

sys/dev/pcmcia/if_ray.c

2040

REG_WRITE(sc, RAY_HCSIR, 0);

sys/dev/pcmcia/if_ray.c

426

#define RAY_ECF_START_CMD(sc) REG_WRITE(sc, RAY_ECFIR, RAY_ECSIR_IRQ)

sys/dev/pcmcia/if_ray.c

543

REG_WRITE(sc, RAY_HCSIR, 0);

sys/dev/pcmcia/if_ray.c

758

REG_WRITE(sc, RAY_HCSIR, 0);