REG_WR - NetBSD

sys/arch/arm/imx/imx23_platform.c

115

REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_RESET, HW_CLKCTRL_RESET_CHIP);

sys/dev/pci/if_bnx.c

1067

REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val);

sys/dev/pci/if_bnx.c

1068

REG_WR(sc, BNX_CTX_CTX_CTRL,

sys/dev/pci/if_bnx.c

1086

REG_WR(sc, BNX_CTX_DATA_ADR, offset);

sys/dev/pci/if_bnx.c

1087

REG_WR(sc, BNX_CTX_DATA, ctx_val);

sys/dev/pci/if_bnx.c

1120

REG_WR(sc, BNX_EMAC_MDIO_MODE, data);

sys/dev/pci/if_bnx.c

1129

REG_WR(sc, BNX_EMAC_MDIO_COMM, data);

sys/dev/pci/if_bnx.c

1162

REG_WR(sc, BNX_EMAC_MDIO_MODE, data);

sys/dev/pci/if_bnx.c

1204

REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);

sys/dev/pci/if_bnx.c

1213

REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);

sys/dev/pci/if_bnx.c

1235

REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);

sys/dev/pci/if_bnx.c

1313

REG_WR(sc, BNX_EMAC_MODE, val);

sys/dev/pci/if_bnx.c

1340

REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);

sys/dev/pci/if_bnx.c

1365

REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2);

sys/dev/pci/if_bnx.c

1401

REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2);

sys/dev/pci/if_bnx.c

1436

REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);

sys/dev/pci/if_bnx.c

1441

REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);

sys/dev/pci/if_bnx.c

1442

REG_WR(sc, BNX_NVM_COMMAND,

sys/dev/pci/if_bnx.c

1479

REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);

sys/dev/pci/if_bnx.c

1501

REG_WR(sc, BNX_NVM_ACCESS_ENABLE,

sys/dev/pci/if_bnx.c

1523

REG_WR(sc, BNX_NVM_ACCESS_ENABLE,

sys/dev/pci/if_bnx.c

1557

REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);

sys/dev/pci/if_bnx.c

1558

REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);

sys/dev/pci/if_bnx.c

1559

REG_WR(sc, BNX_NVM_COMMAND, cmd);

sys/dev/pci/if_bnx.c

1611

REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);

sys/dev/pci/if_bnx.c

1612

REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);

sys/dev/pci/if_bnx.c

1613

REG_WR(sc, BNX_NVM_COMMAND, cmd);

sys/dev/pci/if_bnx.c

1673

REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);

sys/dev/pci/if_bnx.c

1676

REG_WR(sc, BNX_NVM_WRITE, val32);

sys/dev/pci/if_bnx.c

1677

REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);

sys/dev/pci/if_bnx.c

1678

REG_WR(sc, BNX_NVM_COMMAND, cmd);

sys/dev/pci/if_bnx.c

1772

REG_WR(sc, BNX_NVM_CFG1, flash->config1);

sys/dev/pci/if_bnx.c

1773

REG_WR(sc, BNX_NVM_CFG2, flash->config2);

sys/dev/pci/if_bnx.c

1774

REG_WR(sc, BNX_NVM_CFG3, flash->config3);

sys/dev/pci/if_bnx.c

1775

REG_WR(sc, BNX_NVM_WRITE1, flash->write1);

sys/dev/pci/if_bnx.c

2814

REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code);

sys/dev/pci/if_bnx.c

2816

REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code);

sys/dev/pci/if_bnx.c

2821

REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);

sys/dev/pci/if_bnx.c

2824

REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);

sys/dev/pci/if_bnx.c

2830

REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET);

sys/dev/pci/if_bnx.c

2832

REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET);

sys/dev/pci/if_bnx.c

3351

REG_WR(sc, BNX_CTX_COMMAND, val);

sys/dev/pci/if_bnx.c

3368

REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val |

sys/dev/pci/if_bnx.c

3372

REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val);

sys/dev/pci/if_bnx.c

3373

REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i |

sys/dev/pci/if_bnx.c

3399

REG_WR(sc, BNX_CTX_VIRT_ADDR, 0);

sys/dev/pci/if_bnx.c

3400

REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);

sys/dev/pci/if_bnx.c

3406

REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr);

sys/dev/pci/if_bnx.c

3407

REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);

sys/dev/pci/if_bnx.c

3468

REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);

sys/dev/pci/if_bnx.c

3473

REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);

sys/dev/pci/if_bnx.c

3500

REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff);

sys/dev/pci/if_bnx.c

3539

REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS,

sys/dev/pci/if_bnx.c

3550

REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);

sys/dev/pci/if_bnx.c

3578

REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET);

sys/dev/pci/if_bnx.c

3591

REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);

sys/dev/pci/if_bnx.c

3647

REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);

sys/dev/pci/if_bnx.c

3675

REG_WR(sc, BNX_DMA_CONFIG, val);

sys/dev/pci/if_bnx.c

3685

REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,

sys/dev/pci/if_bnx.c

3700

REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);

sys/dev/pci/if_bnx.c

3721

REG_WR(sc, BNX_MQ_CONFIG, val);

sys/dev/pci/if_bnx.c

3724

REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);

sys/dev/pci/if_bnx.c

3725

REG_WR(sc, BNX_MQ_KNL_WIND_END, val);

sys/dev/pci/if_bnx.c

3728

REG_WR(sc, BNX_RV2P_CONFIG, val);

sys/dev/pci/if_bnx.c

3734

REG_WR(sc, BNX_TBDR_CONFIG, val);

sys/dev/pci/if_bnx.c

3767

REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);

sys/dev/pci/if_bnx.c

3773

REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK);

sys/dev/pci/if_bnx.c

3774

REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);

sys/dev/pci/if_bnx.c

3777

REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr));

sys/dev/pci/if_bnx.c

3778

REG_WR(sc, BNX_HC_STATUS_ADDR_H,

sys/dev/pci/if_bnx.c

3782

REG_WR(sc, BNX_HC_STATISTICS_ADDR_L,

sys/dev/pci/if_bnx.c

3784

REG_WR(sc, BNX_HC_STATISTICS_ADDR_H,

sys/dev/pci/if_bnx.c

3788

REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int

sys/dev/pci/if_bnx.c

3790

REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int

sys/dev/pci/if_bnx.c

3792

REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) |

sys/dev/pci/if_bnx.c

3794

REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) |

sys/dev/pci/if_bnx.c

3796

REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) |

sys/dev/pci/if_bnx.c

3798

REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) |

sys/dev/pci/if_bnx.c

3800

REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) |

sys/dev/pci/if_bnx.c

3802

REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00));

sys/dev/pci/if_bnx.c

3803

REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */

sys/dev/pci/if_bnx.c

3804

REG_WR(sc, BNX_HC_CONFIG,

sys/dev/pci/if_bnx.c

3809

REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW);

sys/dev/pci/if_bnx.c

3832

REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);

sys/dev/pci/if_bnx.c

3842

REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);

sys/dev/pci/if_bnx.c

3847

REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,

sys/dev/pci/if_bnx.c

3850

REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT);

sys/dev/pci/if_bnx.c

4292

REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM);

sys/dev/pci/if_bnx.c

4368

REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);

sys/dev/pci/if_bnx.c

4506

REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD,

sys/dev/pci/if_bnx.c

4510

REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD,

sys/dev/pci/if_bnx.c

4517

REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE);

sys/dev/pci/if_bnx.c

4819

REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);

sys/dev/pci/if_bnx.c

4955

REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);

sys/dev/pci/if_bnx.c

4970

REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |

sys/dev/pci/if_bnx.c

4973

REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |

sys/dev/pci/if_bnx.c

4977

REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);

sys/dev/pci/if_bnx.c

5031

REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu |

sys/dev/pci/if_bnx.c

5082

REG_WR(sc, BNX_RV2P_CONFIG, val);

sys/dev/pci/if_bnx.c

5085

REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,

sys/dev/pci/if_bnx.c

5359

REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);

sys/dev/pci/if_bnx.c

5507

REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,

sys/dev/pci/if_bnx.c

5613

REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),

sys/dev/pci/if_bnx.c

5636

REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),

sys/dev/pci/if_bnx.c

5648

REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);

sys/dev/pci/if_bnx.c

5652

REG_WR(sc, BNX_RPM_SORT_USER0, 0x0);

sys/dev/pci/if_bnx.c

5653

REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode);

sys/dev/pci/if_bnx.c

5654

REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA);

sys/dev/pci/if_bnxvar.h

91

#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))

sys/dev/pci/if_bnxvar.h

92

#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))