sys/arch/mips/adm5120/adm5120_intr.c

159

#define REG_WRITE(o,v) (REG_READ(o)) = (v)

sys/arch/mips/adm5120/adm5120_intr.c

220

REG_READ(ICU_MODE_REG) | irqmask);

sys/arch/mips/adm5120/adm5120_intr.c

223

REG_READ(ICU_MODE_REG) & ~irqmask);

sys/arch/mips/adm5120/adm5120_intr.c

275

irqstat = REG_READ(ICU_FIQ_STATUS_REG);

sys/arch/mips/adm5120/adm5120_intr.c

277

irqstat = REG_READ(ICU_STATUS_REG);

sys/arch/mips/adm5120/dev/ahci.c

294

while (REG_READ(ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET)

sys/arch/mips/adm5120/dev/ahci.c

464

if ((REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS) != p0_state) {

sys/arch/mips/adm5120/dev/ahci.c

467

p0_state=(REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS);

sys/arch/mips/adm5120/dev/ahci.c

469

if ((REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS) != p1_state) {

sys/arch/mips/adm5120/dev/ahci.c

472

p1_state=(REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS);

sys/arch/mips/adm5120/dev/ahci.c

677

status = REG_READ(ADMHCD_REG_PORTSTATUS0+(index-1)*4);

sys/arch/mips/adm5120/dev/if_admsw.c

1040

REG_WRITE(ADMSW_INT_MASK, REG_READ(ADMSW_INT_MASK) &

sys/arch/mips/adm5120/dev/if_admsw.c

1147

while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE))

sys/arch/mips/adm5120/dev/if_admsw.c

1157

conf = REG_READ(CPUP_CONF_REG);

sys/arch/mips/adm5120/dev/if_admsw.c

1249

old = REG_READ(PHY_CNTL2_REG);

sys/arch/mips/adm5120/dev/if_admsw.c

1270

status = REG_READ(PHY_ST_REG) >> port;

sys/arch/mips/adm5120/dev/if_admsw.c

254

REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

256

REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP);

sys/arch/mips/adm5120/dev/if_admsw.c

267

REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK);

sys/arch/mips/adm5120/dev/if_admsw.c

284

REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK |

sys/arch/mips/adm5120/dev/if_admsw.c

287

REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);

sys/arch/mips/adm5120/dev/if_admsw.c

302

REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK));

sys/arch/mips/adm5120/dev/if_admsw.c

316

while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE))

sys/arch/mips/adm5120/dev/if_admsw.c

319

wdog1 = REG_READ(ADM5120_WDOG1);

sys/arch/mips/adm5120/dev/if_admsw.c

797

pending = REG_READ(ADMSW_INT_ST);

sys/arch/mips/adm5120/dev/if_admsw.c

946

device_xname(sc->sc_dev), REG_READ(RECV_LBADDR_REG),

sys/arch/mips/adm5120/dev/if_admsw.c

947

REG_READ(RECV_LWADDR_REG), sc->sc_rxptr, i);

sys/arch/mips/adm5120/dev/uart.c

339

if (REG_READ(UART_RSR_REG) & UART_RSR_BE) {

sys/arch/mips/adm5120/dev/uart.c

344

while ((REG_READ(UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) == 0) {

sys/arch/mips/adm5120/dev/uart.c

345

c = REG_READ(UART_DR_REG) & 0xff;

sys/arch/virt68k/dev/virtctrl.c

113

feat = REG_READ(sc, VIRTCTRL_REG_FEATURES);

sys/dev/goldfish/gfpic.c

106

return ffs(REG_READ(sc, GFPIC_PENDING)) - 1;

sys/dev/goldfish/gftty.c

306

while ((count = REG_READ(sc, GFTTY_BYTES_READY)) != 0) {

sys/dev/goldfish/gftty.c

337

count = REG_READ(sc, GFTTY_BYTES_READY);

sys/dev/pcmcia/if_ray.c

2022

if (!REG_READ(sc, RAY_HCSIR))

sys/dev/pcmcia/if_ray.c

425

#define RAY_ECF_READY(sc) (!(REG_READ(sc, RAY_ECFIR) & RAY_ECSIR_IRQ))