Symbol: REGWRITE_2
sys/arch/hpcmips/stand/lcboot/extern.h
103
#define bus_space_write_2(iot, ioh, off, val) REGWRITE_2((ioh), (off), (val))
sys/arch/hpcmips/stand/lcboot/i28f128.c
108
REGWRITE_2(addr, 0, I28F128_WORDBYTE_PROG);
sys/arch/hpcmips/stand/lcboot/i28f128.c
109
REGWRITE_2(addr, 0, data);
sys/arch/hpcmips/stand/lcboot/i28f128.c
115
REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS);
sys/arch/hpcmips/stand/lcboot/i28f128.c
116
REGWRITE_2(addr, 0, I28F128_RESET);
sys/arch/hpcmips/stand/lcboot/i28f128.c
149
REGWRITE_2(dst, 0, I28F128_WRITE_BUFFER);
sys/arch/hpcmips/stand/lcboot/i28f128.c
153
REGWRITE_2(dst, 0, wbuf_count - 1);
sys/arch/hpcmips/stand/lcboot/i28f128.c
156
REGWRITE_2(q, 0, *p);
sys/arch/hpcmips/stand/lcboot/i28f128.c
158
REGWRITE_2(dst, 0, I28F128_WBUF_CONFIRM);
sys/arch/hpcmips/stand/lcboot/i28f128.c
161
REGWRITE_2(dst, 0, I28F128_READ_STATUS);
sys/arch/hpcmips/stand/lcboot/i28f128.c
167
REGWRITE_2(dst, 0, I28F128_CLEAR_STATUS);
sys/arch/hpcmips/stand/lcboot/i28f128.c
168
REGWRITE_2(dst, 0, I28F128_RESET);
sys/arch/hpcmips/stand/lcboot/i28f128.c
65
REGWRITE_2(base, 0, 0x98);
sys/arch/hpcmips/stand/lcboot/i28f128.c
79
REGWRITE_2(base, 0, 0xff);
sys/arch/hpcmips/stand/lcboot/i28f128.c
88
REGWRITE_2(addr, 0, I28F128_BLK_ERASE_1ST);
sys/arch/hpcmips/stand/lcboot/i28f128.c
89
REGWRITE_2(addr, 0, I28F128_BLK_ERASE_2ND);
sys/arch/hpcmips/stand/lcboot/i28f128.c
95
REGWRITE_2(addr, 0, I28F128_CLEAR_STATUS);
sys/arch/hpcmips/stand/lcboot/i28f128.c
96
REGWRITE_2(addr, 0, I28F128_RESET);
sys/arch/hpcmips/stand/lcboot/if_cs.c
75
#define CS_WRITE_2(off, val) REGWRITE_2(CS_IO_BASE, (off), (val))
sys/arch/hpcmips/stand/lcboot/if_cs.c
77
(REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
sys/arch/hpcmips/stand/lcboot/if_cs.c
80
(REGWRITE_2(CS_IO_BASE, PORT_PKTPG_PTR, (off)), \
sys/arch/hpcmips/stand/lcboot/if_cs.c
81
REGWRITE_2(CS_IO_BASE, PORT_PKTPG_DATA, (val)))
sys/arch/hpcmips/stand/lcboot/main.c
188
REGWRITE_2(VRETIMEH, 0, 0);
sys/arch/hpcmips/stand/lcboot/main.c
189
REGWRITE_2(VRETIMEM, 0, 0);
sys/arch/hpcmips/stand/lcboot/main.c
190
REGWRITE_2(VRETIMEL, 0, 0);
sys/arch/hpcmips/stand/lcboot/main.c
213
REGWRITE_2(VR4181_ISABRG_ADDR, ISABRGCTL, 0x0003);
sys/arch/hpcmips/stand/lcboot/main.c
214
REGWRITE_2(VR4181_ISABRG_ADDR, XISACTL, 0x0401);
sys/arch/hpcmips/stand/lcboot/main.c
224
REGWRITE_2(VR4181_CMU_ADDR, 0, CMUMASK_SIU | CMUMASK_AIU);
sys/arch/hpcmips/stand/lcboot/main.c
242
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);
sys/arch/hpcmips/stand/lcboot/main.c
243
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
256
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W, GP8_GPO);
sys/arch/hpcmips/stand/lcboot/main.c
268
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
281
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
298
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PIOD_L_REG_W, 0xffff);
sys/arch/hpcmips/stand/lcboot/main.c
299
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE0_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
314
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE1_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
328
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE2_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
341
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_MODE3_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
356
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTTYP_L_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
358
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTMASK_REG_W,
sys/arch/hpcmips/stand/lcboot/main.c
360
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_INTEN_REG_W, GIEN4);
sys/arch/hpcmips/stand/lcboot/main.c
374
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STRA_REG_W, 0x0000);
sys/arch/hpcmips/stand/lcboot/main.c
375
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0STPA_REG_W, 0x0fff);
sys/arch/hpcmips/stand/lcboot/main.c
376
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCS0HIA_REG_W, 0x1401);
sys/arch/hpcmips/stand/lcboot/main.c
377
REGWRITE_2(VR4181_GIU81_ADDR, VR4181GIU_PCSMODE_REG_W,